Embedded DRAM architecture with local data drivers and programmable number of data read and data write lines

• US 6,166,942 A
• Filed: 01/14/2000
• Issued: 12/26/2000
• Est. Priority Date: 08/21/1998
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Bunker, Layne G., Vo, Huy T., Merritt, Todd A.
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US09/482,912
• Time in Patent Office: 347 Days
• Field of Search: 365/230.03, 365/230.02, 365/230.06, 365/189.01, 365/189.02, 365/51, 365/63
• US Class Current: 365/63
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A DRAM architecture configures memory cells into a predetermined number of arrays. Each array has its own row decoders and sense amplifiers. A data path circuit containing local drivers and data read and write lines is associated with each of the arrays in a first direction. The respective connections between the array and data path circuit utilize IO lines that are considerably shorter than the IO lines used in prior art architectures. Using this unique arrangement of data path circuits and memory arrays as a building block, a DRAM architecture of increased capacity can be constructed by simply placing additional data paths and memory arrays on to the semiconductor device in a second direction orthogonal to the first direction.

Claims

1. A memory circuit comprising:

a first pair of transfer circuits arranged adjacent to each other in a first direction, each transfer circuit being connected to a respective input circuit and output circuit; and

at least one block of memory cells connected to each transfer circuit, each block of memory cells being arranged in said first direction with respect to its associated transfer circuit, said blocks of memory cells being arranged such that said first pair of transfer circuits and their associated input and output circuits are located between said blocks of memory cells with respect to said first direction, each transfer circuit for transferring data between its associated input and output circuits and block of memory cells.

2. The memory circuit of claim 1, wherein each block of memory cells comprises:

a plurality of word lines, each of said word lines being respectively connected to a row of memory cells of said block;

a plurality of digit lines, each of said digit lines being respectively connected to a column of memory cells of said block;

at least one row decoder, each of said row decoders connected to said word lines of said block; and

a plurality of sense amplifier circuits for reading data from and writing data to said memory cells, said sense amplifier circuits being respectively connected to said digit lines of said block, said sense amplifier circuits having a plurality of data transferring lines for transferring data between a respective one of said input and output circuits and said sense amplifier circuits.

3. The memory circuit of claim 2, wherein each input circuit comprises a plurality of write driver circuits connectable to said sense amplifier circuits, each of said write driver circuits having a data write line for inputting data into said sense amplifier circuits.

4. The memory circuit of claim 2, wherein each output circuit comprises a plurality of read driver circuits connectable to said sense amplifier circuits, each of said read driver circuits having a data read line for outputting data from said sense amplifier circuits.

5. The memory circuit of claim 2, wherein each block of memory cells includes two row decoders located on opposite sides of said block, said row decoders respectively activating alternate word lines within a block.

6. The memory circuit of claim 1, wherein each transfer circuit and its associated input and output circuits are associated with and positioned adjacent to two of said blocks of memory cells in said first direction, both of said blocks of memory being on a same side of an associated transfer circuit.

7. The memory circuit of claim 6, wherein each transfer circuit and its associated input and output circuits are associated with at least another two of said blocks of memory cells in a second direction orthogonal to said first direction.

8. The memory circuit of claim 7, wherein each transfer circuit comprises a section select circuit coupled to sense amplifier circuitry of its associated blocks of memory cells and wherein each section select circuit selectively couples sense amplifier circuits from adjacent blocks of memory cells arranged in said second direction to a input or output circuits associated with one of said adjacent blocks.

9. The memory circuit of claim 1, wherein each transfer circuit and its associated input and output circuits are associated with and positioned adjacent to four of said blocks of memory in said first direction, all four of said blocks of memory being on a same side of an associated transfer circuit.

10. The memory circuit of claim 9, wherein each transfer circuit and its associated input and output circuits are associated with at least another four of said blocks of memory cells in a second direction orthogonal to said first direction.

11. The memory circuit of claim 10, wherein each transfer circuit comprises a section select circuit coupled to sense amplifier circuitry of its associated blocks of memory cells and wherein each section select circuit selectively couples sense amplifier circuits from adjacent blocks of memory cells arranged in said second direction to a input or output circuits associated with one of said adjacent blocks.

12. A memory circuit comprising:

a first block of memory cells connected to a first input circuit and a first output circuit through a first transfer circuit, said first input, output and transfer circuits being positioned adjacent said first block of memory cells in a first direction and being on a same side of said first block of memory cells; and

a second block of memory cells connected to a second input circuit and a second output circuit through a second transfer circuit, said second input, output and transfer circuits being positioned adjacent said second block of memory cells in said first direction and being on a same side of said second block of memory cells such that said first and second input, output and transfer circuits are positioned between said first and second blocks of memory cells with respect to said first direction.

13. The memory circuit of claim 12, wherein each block of memory cells comprises:

a plurality of word lines, each of said word lines being respectively connected to a row of memory cells of said block;

a plurality of digit lines, each of said digit lines being respectively connected to a column of memory cells of said block;

at least one row decoder, each of said row decoders connected to said word lines of said block; and

a plurality of sense amplifier circuits for reading data from and writing data to said memory cells, said sense amplifier circuits being respectively connected to said digit lines of said block, said sense amplifier circuits having a plurality of data transferring lines for transferring data between a respective one of said input and output circuits and said sense amplifier circuits.

14. The memory circuit of claim 13, wherein each input circuit comprises a plurality of write driver circuits connectable to said sense amplifier circuits, each of said write driver circuits having a data write line for inputting data into said sense amplifier circuits.

15. The memory circuit of claim 13, wherein each output circuit comprises a plurality of read driver circuits connectable to said sense amplifier circuits, each of said read driver circuits having a data read line for outputting data from said sense amplifier circuits.

16. The memory circuit of claim 13, wherein each block of memory cells includes two row decoders located on opposite sides of said block, said row decoders respectively activating alternate word lines within a block.

17. The memory circuit of claim 12 further comprising two additional blocks of memory cells, one of said additional blocks of memory cells being connected to said first input and output circuits through said first transfer circuit and being positioned adjacent said first block of memory cells with respect to said first direction, another of said additional blocks of memory cells being connected to said second input and output circuits through said second transfer circuit and being positioned adjacent said second block of memory cells with respect to said first direction such that said first and second input, output and transfer circuits are positioned between said first, second and additional blocks of memory cells with respect to said first direction.

18. The memory circuit of claim 12 further comprising two additional blocks of memory cells, one of said additional blocks of memory cells being connected to said first input and output circuits through said first transfer circuit and being positioned adjacent said first block of memory cells in a second direction, another of said additional blocks of memory cells being connected to said second input and output circuits through said second transfer circuit and being positioned adjacent said second block of memory cells in said second direction such that said input, output and transfer circuits are positioned between said first, second and additional blocks of memory cells with respect to said first direction.

19. The memory circuit of claim 12 further comprising six additional blocks of memory cells, three of said additional blocks of memory cells being connected to said first input and output circuits through said first transfer circuit and being positioned adjacent said first block of memory cells with respect to said first direction, another three of said additional blocks of memory cells being connected to said second input and output circuits through said second transfer circuit and being positioned adjacent said second block of memory cells with respect to said first direction such that said first and second input, output and transfer circuits are positioned between said first, second and additional blocks of memory cells with respect to said first direction.

20. The memory circuit of claim 19 further comprising another eight blocks of memory cells, four of said another eight blocks of memory cells being connected to said first input and output circuits through said first transfer circuit and being positioned adjacent said first block of memory cells in a second direction, another four of said another eight blocks of memory cells being connected to said second input and output circuits through said second transfer circuit and being positioned adjacent said second block of memory cells in said second direction such that said input, output and transfer circuits are positioned between said first, second and additional blocks of memory cells with respect to said first direction.

21. A computer system comprising:

a processor; and

a semiconductor device connected to said processor, said semiconductor device comprised of memory modules connected to a column decoder, each of said memory modules comprising;

a first pair of transfer circuits arranged adjacent to each other in a first direction, each transfer circuit being connected to a respective input circuit and output circuit; and

at least one block of memory cells connected to each transfer circuit, each block of memory cells being arranged in said first direction with respect to its associated transfer circuit, said blocks of memory cells being arranged such that said first pair of transfer circuits and their associated input and output circuits are located between said blocks of memory cells with respect to said first direction, each transfer circuit for transferring data between its associated input and output circuits and block of memory cells.

22. The system of claim 21, wherein each block of memory cells comprises:

a plurality of word lines, each of said word lines being respectively connected to a row of memory cells of said block;

a plurality of digit lines, each of said digit lines being respectively connected to a column of memory cells of said block;

at least one row decoder, each of said row decoders connected to said word lines of said block; and

a plurality of sense amplifier circuits for reading data from and writing data to said memory cells, said sense amplifier circuits being respectively connected to said digit lines of said block, said sense amplifier circuits having a plurality of data transferring lines for transferring data between a respective one of said input and output circuits and said sense amplifier circuits.

23. The system of claim 22, wherein each input circuit comprises a plurality of write driver circuits connectable to said sense amplifier circuits, each of said write driver circuits having a data write line for inputting data into said sense amplifier circuits.

24. The system of claim 22, wherein each output circuit comprises a plurality of read driver circuits connectable to said sense amplifier circuits, each of said read driver circuits having a data read line for outputting data from said sense amplifier circuits.

25. The system of claim 22, wherein each block of memory cells includes two row decoders located on opposite sides of said block, said row decoders respectively activating alternate word lines within a block.

26. The system of claim 21, wherein each transfer circuit and its associated input and output circuits are associated with and positioned adjacent to two of said blocks of memory cells in said first direction, both of said blocks of memory being on a same side of an associated transfer circuit.

27. The system of claim 26, wherein each transfer circuit and its associated input and output circuits are associated with at least another two of said blocks of memory cells in a second direction orthogonal to said first direction.

28. The system of claim 27, wherein each transfer circuit comprises a section select circuit coupled to sense amplifier circuitry of its associated blocks of memory cells and wherein each section select circuit selectively couples sense amplifier circuits from adjacent blocks of memory cells arranged in said second direction to a input or output circuits associated with one of said adjacent blocks.

29. The system of claim 21, wherein each transfer circuit and its associated input and output circuits are associated with and positioned adjacent to four of said blocks of memory in said first direction, all four of said blocks of memory being on a same side of an associated transfer circuit.

30. The system of claim 29, wherein each transfer circuit and its associated input and output circuits are associated with at least another four of said blocks of memory cells in a second direction orthogonal to said first direction.

31. The system of claim 30, wherein each transfer circuit comprises a section select circuit coupled to sense amplifier circuitry of its associated blocks of memory cells and wherein each section select circuit selectively couples sense amplifier circuits from adjacent blocks of memory cells arranged in said second direction to a input or output circuits associated with one of said adjacent blocks.

32. The system of claim 21 wherein at least two memory modules are connected to said column decoder and are positioned on the semiconductor device in a second direction orthogonal to a first direction.

33. The system of claim 21 wherein at least four memory modules are connected to said column decoder and are positioned on the semiconductor device in a second direction orthogonal to a first direction.

34. The system of claim 33 wherein said at least four memory modules are configured into two columns in a first direction.

35. The system of claim 21 wherein at least eight memory modules are connected to said column decoder and are positioned on the semiconductor device in a second direction orthogonal to a first direction.

36. The system of claim 35 wherein said at least eight memory modules are configured into two columns in a first direction.

37. A method of operating a memory circuit comprising a first data read circuit connected to at least first and second memory arrays by a first selection circuit, said method comprising:

propagating a signal to cause the first selection circuit to connect the first memory array to the first data read circuit;

propagating a signal to activate a first word line connected to a row of memory cells in the first memory array;

propagating a signal to activate at least a first digit line connected to a column of memory cells in the first memory array having the first word line activated;

transferring data from memory cells associated with and connected to the activated first word line and first digit line;

propagating a signal to cause the first selection circuit to connect the second memory array to the first data read circuit;

propagating a signal to activate a second word line connected to a row of memory cells in the second memory array;

propagating a signal to activate at least a second digit line connected to a column of memory cells in the second memory array having the second word line activated; and

transferring data from memory cells associated with and connected to the activated second word line and second digit line.

38. The method of claim 37, wherein the memory circuit comprises a second data read circuit connected to the first and second memory arrays by a second selection circuit, said method farther comprises the steps of:

propagating a signal to cause the second selection circuit to connect the first memory array to the second data read circuit;

propagating a signal to activate a third word line connected to a row of memory cells in the first memory array;

propagating a signal to activate at least a third digit line connected to a column of memory cells in the first memory array having the third word line activated; and

transferring data from memory cells associated with and connected to the activated third word line and third digit line.

39. The method of claim 37, wherein the memory circuit comprises a second data read circuit connected to the first and second memory arrays by a second selection circuit, said method further comprises the steps of:

propagating a signal to cause the second selection circuit to connect the second memory array to the second data read circuit;

propagating a signal to activate a third word line connected to a row of memory cells in the second memory array;

propagating a signal to activate at least a third digit line connected to a column of memory cells in the second memory array having the third word line activated; and

transferring data from memory cells associated with and connected to the activated third word line and third digit line.

40. A method of operating a memory circuit comprising a first data write circuit connected to at least first and second memory arrays by a first selection circuit, said method comprising:

propagating a signal to cause the first selection circuit to connect the first memory array to the first data write circuit;

propagating a signal to activate a first word line connected to a row of memory cells in the first memory array;

propagating a signal to activate at least a first digit line connected to a column of memory cells in the first memory array having the first word line activated;

transferring data to memory cells associated with and connected to the activated first word line and first digit line;

propagating a signal to cause the first selection circuit to connect the second memory array to the first data write circuit;

propagating a signal to activate a second word line connected to a row of memory cells in the second memory array;

propagating a signal to activate at least a second digit line connected to a column of memory cells in the second memory array having the second word line activated; and

transferring data to memory cells associated with and connected to the activated second word line and second digit line.

41. The method of claim 40, wherein the memory circuit comprises a second data write circuit connected to the first and second memory arrays by a second selection circuit, said method further comprises the steps of:

propagating a signal to cause the second selection circuit to connect the first memory array to the second data write circuit;

propagating a signal to activate a third word line connected to a row of memory cells in the first memory array;

propagating a signal to activate at least a third digit line connected to a column of memory cells in the first memory array having the third word line activated; and

transferring data to memory cells associated with and connected to the activated third word line and third digit line.

42. The method of claim 40, wherein the memory circuit comprises a second data write circuit connected to the first and second memory arrays by a second selection circuit, said method further comprises the steps of:

propagating a signal to cause the second selection circuit to connect the second memory array to the second data write circuit;

propagating a signal to activate a third word line connected to a row of memory cells in the second memory array;

propagating a signal to activate at least a third digit line connected to a column of memory cells in the second memory array having the third word line activated; and

transferring data to memory cells associated with and connected to the activated third word line and third digit line.