Method, system and apparatus for determining that a programming voltage level is sufficient for reliably programming an eeprom

• US 6,166,960 A
• Filed: 09/24/1999
• Issued: 12/26/2000
• Est. Priority Date: 09/24/1999
• Status: Expired due to Term

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Chen, Meiling, Smit, Willem, Marneweck, Willem J.
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US09/405,450
• Time in Patent Office: 459 Days
• Field of Search: 365/189.09, 365/226, 365/228, 365/229, 365/185.24, 365/185.28, 365/185.18
• US Class Current: 365/185.28
• CPC Class Codes: G11C 16/225 Preventing erasure, programming or reading when power supply voltages are outside the required ranges
• CPC Class Codes: G11C 16/30 Power supply circuits

Abstract

An electronic system, comprising a digital processor and an EEPROM, has circuit logic and program software or firmware for determining if a programming voltage level is sufficient for reliably programming the EEPROM. A charge pump is enabled and generates a voltage used for programming of the EEPROM. The enabled charge pump thereby loads a battery power supply. In addition, a test load may be connected to the output of the charge pump to simulate the EEPROM load during a programming operation to the EEPROM. The charge pump output voltage is measured to determine if at least a desired voltage value is obtained. Once the charge pump voltage level has been pre-qualified for the desired voltage value, an actual programming operation to the EEPROM may be performed. If the voltage level does not reach the desired value then a programming operation is inhibited and the electronic system may alarm or shut down operation. The charge pump voltage level is a good indication and measure of battery charge condition under actual EEPROM programming load conditions.

Claims

1. An electronic system having an electrically erasable programmable read only memory (EEPROM), said system comprising:

a processor;

an analog-to-digital converter (ADC);

an EEPROM;

EEPROM programming logic; and

a charge pump for generating an EEPROM programming voltage;

wherein the EEPROM programming voltage generated by said charge pump is converted from an analog value to a digital value by said ADC and the digital value of the EEPROM programming voltage is read by said processor to determine if the digital value is equal to or greater than a desired value;

whereby,

if the generated EEPROM programming voltage is equal to or greater than the desired value then said EEPROM programming logic is enabled to perform a programming operation on said EEPROM; and

if the generated EEPROM programming voltage is less than the desired value then said EEPROM programming logic is inhibited from performing a programming operation on said EEPROM.

2. The system of claim 1, further adapted for connection to a battery power supply.

3. The system of claim 1, wherein said EEPROM programming logic performs a plurality of programming operations on said EEPROM once the EEPROM programming voltage has been determined to be equal to or greater than the desired value.

4. The system of claim 1, wherein said EEPROM programming logic performs one programming operation on said EEPROM after each time the EEPROM programming voltage has been determined to be equal to or greater than the desired value.

5. The system of claim 1, further comprising a random access memory (RAM), a read only memory (ROM) and input-output (I/O) interface circuits connected to said processor.

6. The system of claim 5, wherein said processor, EEPROM, EEPROM programming logic, charge pump, RAM, ROM and I/O interface circuits are fabricated on a single integrated circuit.

7. The system of claim 5, wherein said processor, EEPROM, EEPROM programming logic, charge pump, RAM, ROM and I/O interface circuits are fabricated on a plurality of integrated circuits.

8. The system of claim 7, wherein said plurality of integrated circuits are interconnected with a wiring substrate selected from the group consisting of a printed circuit board and a printed wiring board.

22. The system of claim 1, wherein the logic for enabling said charge pump is said processor controlled by a software program.

23. The system of claim 1, wherein the logic for enabling said charge pump is an application specific circuit logic.

24. The system of claim 23, wherein the application specific circuit logic is controlled by firmware.

25. The system of claim 1, wherein the logic for enabling said charge pump is said processor controlled by firmware.

26. The system of claim 1, further comprising a test load connected to said charge pump when determining if the generated EEPROM programming voltage is equal to or greater than the desired value.

27. The system of claim 26, wherein said test load is connected to said charge pump by addressing said test load outside of said EEPROM address space.

28. The system of claim 6, wherein the processor is microcontroller core logic.

29. The system of claim 1, wherein the processor is a microprocessor.

30. The system of claim 1, wherein the processor is a plurality of microprocessors.

31. The system of claim 1, wherein the processor is a digital signal processor.

32. The system of claim 1, wherein the processor comprises digital logic.

33. The system of claim 1, wherein the processor comprises a programmable logic array.

34. The system of claim 1, wherein the EEPROM is flash ROM.

40. The system of claim 1, wherein the processor is a microcontroller.

9. A method for preventing soft programming to an electrically erasable programmable read only memory (EEPROM) in an electronic system, said method comprising the steps of:

generating an EEPROM programming voltage;

determining with an analog-to-digital converter (ADC) and a processor if the generated EEPROM programming voltage is equal to or greater than a desired value;

if so, enabling an EEPROM programming logic for programming an EEPROM, and

if not, disabling the EEPROM programming logic to prevent programming the EEPROM.

10. The method of claim 9, wherein the step of generating an EEPROM programming voltage is done with a charge pump.

11. The method of claim 9, after the step of enabling the EEPROM programming logic, further comprising the step of performing a single programming operation to the EEPROM.

12. The method of claim 9, after the step of enabling the EEPROM programming logic, further comprising the step of performing a plurality of programming operations to the EEPROM.

13. The method of claim 11, after the step of performing a single programming operation to the EEPROM, further comprising repeating the steps of determining if the generated EEPROM programming voltage is equal to or greater than the desired value, enabling the EEPROM programming logic and performing a single programming operation until all data has been written to the EEPROM.

35. The method of claim 9, wherein the step of generating an EEPROM programming voltage further comprises the step of applying a test load to the generated EEPROM programming voltage.

36. The method of claim 35, wherein the step of applying a test load comprises the step of addressing the test load outside of the EEPROM address space.

14. A method for programming an electrically erasable programmable read only memory (EEPROM) in an electronic system, said method comprising the steps of:

generating an EEPROM programming voltage by switching on a charge pump;

determining with an analog-to-digital converter (ADC) and a processor if the generated EEPROM programming voltage is equal to or greater than a desired value;

if so, turning off the charge pump and continuing normal operation of the electronic system, and

if not, turning off the charge pump and alerting the electronic system of a low generated EEPROM programming voltage.

15. The method of claim 14, after the step of continuing normal operation of the electronic system, further comprising the steps of:

switching on the charge pump for generating the EEPROM programming voltage; and

programming the EEPROM.

16. The method of claim 14, wherein the step of alerting the electronic system of a low generated EEPROM programming voltage includes the step of shutting down the electronic system.

37. The method of claim 14, wherein the step of generating an EEPROM programming voltage further comprises the step of applying a test load to the generated EEPROM programming voltage.

17. A method for programming an electrically erasable programmable read only memory (EEPROM) in an electronic system, said method comprising the steps of:

(a) generating an EEPROM programming voltage by switching on a charge pump;

(b) determining with an analog-to-digital converter (ADC) and a processor if the generated EEPROM programming voltage is equal to or greater than a desired voltage value;

(c) if so, doing a single programming operation to the EEPROM and then returning to step (b) until all pending programming operations to the EEPROM are finished, and

(d) if not, turning off the charge pump and alerting the electronic system of a low generated EEPROM programming voltage.

38. The method of claim 17, wherein the step of generating an EEPROM programming voltage further comprises the step of applying a test load to the generated EEPROM programming voltage.

18. A method for programming an electrically erasable programmable read only memory (EEPROM) in an electronic system, said method comprising the steps of:

(a) generating an EEPROM programming voltage by switching on a charge pump;

(b) determining with an analog-to-digital converter (ADC) and a processor if the generated EEPROM programming voltage is equal to or greater than a desired voltage value;

(c) if so, doing a plurality of programming operations to the EEPROM until all pending programming operations to the EEPROM are finished, and

(d) if not, turning off the charge pump and alerting the electronic system of a low generated EEPROM programming voltage.

39. The method of claim 18, wherein the step of generating an EEPROM programming voltage further comprises the step of applying a test load to the generated EEPROM programming voltage.

19. An apparatus for preventing soft programming to an electrically erasable programmable read only memory (EEPROM), said apparatus comprising:

a charge pump for generating an EEPROM programming voltage;

an analog-to-digital converter (ADC) and a processor for determining if the generated EEPROM programming voltage is at least a desired voltage level; and

a circuit adapted to inhibit EEPROM programming logic if the EEPROM programming voltage is not at least the desired voltage level.

20. The apparatus of claim 19, further comprising an alarm signal for alerting an electronic system when the EEPROM programming voltage is not at least the desired voltage level.

21. The apparatus of claim 19, further adapted for connection to a battery power supply.

48. The apparatus of claim 19, further comprising a test load connected to said charge pump when determining if the generated EEPROM programming voltage is equal to or greater than the desired value.

41. An electronic system having an electrically erasable programmable read only memory (EEPROM), said system comprising:

an EEPROM;

EEPROM programming logic;

a test load; and

a charge pump for generating an EEPROM programming voltage;

wherein, said test load is connected to said charge pump when the generated EEPROM programming voltage is being measured to determine if it is equal to or greater than a desired value;

whereby,

if the generated EEPROM programming voltage is equal to or greater than the desired value then said EEPROM programming logic is enabled to perform a programming operation on said EEPROM; and

if the generated EEPROM programming voltage is less than the desired value then said EEPROM programming logic is inhibited from performing a programming operation on said EEPROM.

42. A method for preventing soft programming to an electrically erasable programmable read only memory (EEPROM) in an electronic system, said method comprising the steps of:

generating an EEPROM programming voltage;

applying a test load to the generated EEPROM programming voltage when determining if the generated EEPROM programming voltage is equal to or greater than a desired value;

if so, enabling an EEPROM programming logic for programming an EEPROM without applying the test load, and

if not, disabling the EEPROM programming logic to prevent programming the EEPROM.

43. A method for programming an electrically erasable programmable read only memory (EEPROM) in an electronic system, said method comprising the steps of:

generating an EEPROM programming voltage by switching on a charge pump;

applying a test load to the generated EEPROM programming voltage when determining if the generated EEPROM programming voltage is equal to or greater than a desired voltage value;

if so, turning off the charge pump and continuing normal operation of the electronic system, and

if not, turning off the charge pump and alerting the electronic system of a low generated EEPROM programming voltage.

44. The method of claim 43, after the step of continuing normal operation of the electronic system, further comprising the steps of:

switching on the charge pump for generating the EEPROM programming voltage without applying the test load; and

programming the EEPROM.

45. A method for programming an electrically erasable programmable read only memory (EEPROM) in an electronic system, said method comprising the steps of:

(a) generating an EEPROM programming voltage by switching on a charge pump;

(b) applying a test load to the generated EEPROM programming voltage when determining if the generated EEPROM programming voltage is equal to or greater than a desired voltage value;

(c) if the generated EEPROM programming voltage is equal to or greater than a desired voltage value, then doing a single programming operation to the EEPROM and returning to step (b) until all pending programming operations to the EEPROM are finished, and

(d) if not, turning off the charge pump and alerting the electronic system of a low generated EEPROM programming voltage.

46. A method for programming an electrically erasable programmable read only memory (EEPROM) in an electronic system, said method comprising the steps of:

(a) generating an EEPROM programming voltage by switching on a charge pump;

(b) applying a test load to the generated EEPROM programming voltage when determining if the generated EEPROM programming voltage is equal to or greater than a desired voltage value;

(c) if the generated EEPROM programming voltage is equal to or greater than a desired voltage value, then doing a plurality of programming operations to the EEPROM and, and

(d) if not, turning off the charge pump and alerting the electronic system of a low generated EEPROM programming voltage.

47. An apparatus for preventing soft programming to an electrically erasable programmable read only memory (EEPROM), said apparatus comprising:

a charge pump for generating an EEPROM programming voltage;

a circuit for determining if the generated EEPROM programming voltage is at least a desired voltage level;

a test load, said test load being connected to the charge pump generated EEPROM programming voltage when determining if the generated EEPROM programming voltage is at least the desired voltage level; and

a circuit adapted to inhibit EEPROM programming logic if the EEPROM programming voltage is not at least the desired voltage level.