Circuit and method for conditioning flash memory array

• US 6,166,962 A
• Filed: 06/24/1999
• Issued: 12/26/2000
• Est. Priority Date: 06/24/1999
• Status: Expired due to Fees

• Current Assignee: AMIC Technology Corporation
• Original Assignee: AMIC Technology Corporation
• Inventors: Fu, Shih-Chun, Chan, Jui-Te, Chen, Kou-Su
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, THONG QUOC
• Application Number:
  US09/344,316
• Time in Patent Office: 551 Days
• Field of Search: 365/185.33, 365/185.14, 365/185.29, 365/185.3, 365/191, 365/185.24
• US Class Current: 365/185.3
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
• CPC Class Codes: G11C 16/3477 Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing

Abstract

A novel cell conditioning mechanism is employed to equalize charge discharge characteristics of flash memory cells. A variable conditioning signal removes charge from "fast" bits in the array, and leaves other cells relatively unaffected so that the fast bits are adjusted to have threshold voltages closer to those of the other cells in an array. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.

Claims

1. A method of preventing over-erasure of a flash cell in a memory arras from an erase operation, said method comprising:

(a) generating a plurality of separate conditioning signals in a predetermined time sequence, wherein a magnitude of said separate plurality of conditioning signals is varied during said predetermined time sequence; and

(b) progressively removing charge from the flash cell using said separate plurality of conditioning signals, said charge being insufficient to place such flash cell in a fully erased state; and

wherein erase speed characteristics of flash cells in the array are substantially equalized prior to an erase operation so that the probability of an occurrence of an over-erased flash cell is reduced.

2. The method of claim 1, further including a step (c):

applying a bias voltage to a first and a second well regions associated with the array while said plurality of conditioning signals are applied to the array.

3. The method of claim 1, wherein steps (a) and (b) counteract non-uniformities in electrical field intensities across tunnel oxides for flash cell in the array.

4. The method of claim 1, wherein characteristics of said plurality of conditioning signals can be adjusted while the memory array is being manufactured to tailor such characteristics to the requirements of cells in the flash memory.

5. A method of reducing electrical field intensity variations caused by manufacturing deviations in tunnel oxide layers associated with flash cells in a memory array, said method comprising:

(a) generating a plurality of separate flash cell conditioning signals, wherein signal characteristics of said plurality of separate flash cell conditioning signals are varied in time; and

(b) adjusting initial electrical field intensity values across a tunnel oxide layer of each of said flash cells using said plurality of separate flash cell conditioning signals;

wherein flash cells with electrical field intensity values across an associated tunnel oxide that are substantially greater than a target electrical field intensity value are substantially adjusted by said plurality of separate flash cell conditioning signals during step (b), while other flash cells in said memory array are substantially unaffected during step (b) by said plurality of separate flash cell conditioning signals; and

further wherein initial electrical field intensity variations for each of the flash cells in the memory array caused by manufacturing deviations are substantially compensated for by said plurality of separate flash cell conditioning signals, and the electrical field intensities across each of the tunnel oxides for the flash cells are made approximately equal.

6. The method of claim 5, wherein a bias voltage is applied to a first and a second well regions associated with said memory array while said plurality of separate flash cell conditioning signals are applied to said memory array.

7. The method of claim 5, wherein said plurality of separate flash cell conditioning signals operate to remove charge from, or add electrical charge to, floating gates of said flash cells.

8. The method of claim 5, wherein discharge characteristics of said flash cells are made more uniform by said plurality of separate flash cell conditioning signals.

9. The method of claim 5, wherein characteristics of said plurality of separate flash cell conditioning signals can be adjusted while the memory array is being manufactured to tailor such characteristics to the manufacturing deviations present for such cells in the flash memory.

10. A method of partially erasing a portion of a flash memory cell array, the method including the steps of:

(a) generating a partial erase signal having a magnitude and a duration configured to affect substantially less electrical charge in said cells than that electrical charge affected by a normal erase cycle for the array; and

(b) applying said partial erase signal to said cells in the flash memory cell array;

(c) measuring a threshold voltage Vt of each of said cells after said partial erase signal is applied to determine if said threshold voltage Vt is substantially within predetermined target values; and

(d) repeating steps (a) and (b) by increasing said magnitude and/or said duration of said partial erase signal so that a plurality of separate partial erase signals are generated in a predetermined time sequence; and

(e) repeating step (c) after step (d);

wherein steps (a) through (e) are repeated as needed to cause said threshold voltages of said cells to converge to said predetermined target values.

11. The method of claim 10, further including a step (f):

applying a bias voltage to a first and a second well regions associated with said flash memory cell array while said plurality of separate partial erase are applied to said flash memory cell array.

12. The method of claim 10, wherein said plurality of separate partial erase signals operate to remove charge from, or add electrical charge to, floating gates of said flash cells.

13. The method of claim 10, wherein discharge characteristics of said flash cells are made more uniform by said plurality of separate partial erase signals.

14. The method of claim 10, wherein characteristics of said plurality of separate partial erase signals can be adjusted while the memory array is being manufactured to tailor such characteristics to the manufacturing deviations present for such cells in the flash memory.

15. A method of equalizing electrical charge discharge characteristics of flash cells in a memory array, such flash cells including a tunnel oxide that is utilized for Fowler-Nordheim tunneling to place such flash cells in an erased state during an erase operation, the method including the steps of:

(a) generating a conditioning signal that is configured to reduce an electrical field across the tunnel oxide of said flash cells, but which is also insufficient to place said cells into an erased state;

(b) applying said conditioning signal to said flash cells while said flash cells have a threshold voltage corresponding to a non-erased state;

(c) measuring said threshold voltage Vt of each of said flash cells after said conditioning signal is applied to determine if each of said threshold voltages Vt have been reduced below a target threshold value Vtmax; and

(d) terminating said conditioning signal unless any of said flash cells have threshold voltages Vt exceeding Vtmax, in which case steps (a) and (b) are repeated using a conditioning signal configured to further reduce said electric field;

(e) repeating step (c) if steps (a) and (b) are repeated;

wherein steps (a) through (e) are repeated as desired to cause said threshold voltages of said cells to fall below said target threshold value Vtmax.

16. The method of claim 15, wherein a bias voltage is applied to a first and a second well region associated with said memory array while said conditioning signals are applied.

17. The method of claim 15, wherein said conditioning signal operates to remove charge from, or add electrical charge to, floating gates of said flash cells.

18. The method of claim 15, wherein discharge characteristics of said flash cells are made more uniform by said conditioning signal.

19. The method of claim 15, wherein characteristics of said conditioning signal can be adjusted while the memory array is being manufactured to tailor such characteristics to manufacturing deviations present for such cells in the flash memory.

20. The method of claim 15, wherein a probability of any flash cell becoming over-erased during an erase operation is reduced.