Switch with flexible link list manager for handling ATM and STM traffic

• US 6,167,041 A
• Filed: 03/17/1998
• Issued: 12/26/2000
• Est. Priority Date: 03/17/1998
• Status: Expired due to Term

• Current Assignee: Afanador J. Abraham
• Original Assignee: Afanador J. Abraham
• Inventors: Afanador, J. Abraham
• Primary Examiner(s): Kizou, Hassan
• Assistant Examiner(s): Elallam, Ahmed
• Application Number:
  US09/040,080
• Time in Patent Office: 1,015 Days
• Field of Search: 370/352, 370/353, 370/356, 370/389, 370/390, 370/395, 370/412, 370/413, 370/414, 370/419
• US Class Current: 370/353
• CPC Class Codes: H04J 2203/001 using a shared central buffer
• CPC Class Codes: H04L 12/6402 Hybrid switching fabrics
• CPC Class Codes: H04L 2012/5651 Priority, marking, classes
• CPC Class Codes: H04L 2012/5679 Arbitration or scheduling
• CPC Class Codes: H04L 49/108 using shared central buffer
• CPC Class Codes: H04L 49/606 Hybrid ATM switches, e.g. ATM&STM, ATM&Frame Relay or ATM&IP

Abstract

A telecommunication switch for handling both synchronous transfer mode (STM) digital data signals and asynchronous transfer mode (ATM) digital data signals includes a flexible link list manager for mapping input slots to output slots, an input hybrid page, an output hybrid page and a hybrid routing table for managing the time slot interchange function. The STM data stream is segmented to form fixed length, serially propagating digital data words. The segment length of each STM data word is equal to the ATM cell length. The number of bytes in each STM segment and the number of bytes in each ATM cell are the same, and the STM segments and ATM cells are equal in duration. Because the ATM and STM signals are routed through a common switch, it is not necessary to split the two types of traffic before switching can be performed. Consequently, the switch can support any network distribution of ATM and STM traffic with the same switching equipment.

Claims

1. A switch for handling synchronous transfer mode (STM) digital data signals and asynchronous transfer mode (ATM) digital data signals, comprising:

at least two digital data input links, wherein at least one data input link is configured for handling data bits propagating synchronously in a serial stream and at least one data input link is configured for handling data bits propagating asynchronously in a serial stream;

an input memory page including an input memory and at least two input registers coupled to the input links for accumulating digital data segments each having an equal number of bits taken from each serial input link, respectively, and outputting the data segments in parallel format into the input memory;

a data buffer coupled to the input memory for storing the parallel format data segments;

at least two digital data output links, wherein at least one output link is configured for handling data bits propagating synchronously in a serial stream and at least one output link is configured for handling data bits propagating asynchronously in a serial stream;

an output memory page including an output memory and at least two output registers coupled to the data buffer for receiving parallel format data segments from the data buffer, accumulating the data segments in serial format, and outputting the data segments in serial format on predetermined ones of the digital data output links; and

,

a link list manager coupled to the data buffer for coordinating the flow of data into and out of the data buffer.

2. A switch as set forth in claim 1, the link list manager comprising a programmable memory for storing a link list logic table, a virtual path identifier/virtual channel identifier table, at least two output queues, and a routing table.

3. A switch as set forth in claim 1 further comprising a page combiner module coupled to the data buffer for performing byte-wise parallel-to-serial conversion of data stored in the data buffer.

4. A switch set forth in of claim 1 including two or more output queues, a head of queue register, a tail of queue register and a depth of queue register coupled to the link list manager for directing synchronous transfer mode digital data from the at least one STM data input link to at least one output queue of depth one, the at least one output queue of depth one being coupled to the at least one STM data output link.

5. A switch as set forth in claim 1 including two or more output queues, a head of queue register, a tail of queue register and a depth of queue register coupled to the link list manager for directing asynchronous transfer mode digital data from at least one ATM data input link to at least one output queue of depth one or more, the at least one output queue of depth one or more being coupled to the at least one ATM data output link.

6. A switch as set forth in claim 5, wherein the at least one ATM data link having a bandwidth, and including a priority tournament resolution manager for distributing the bandwidth among a plurality of classes of service.

7. A switch as set forth in claim 6, the plurality of classes of service being associated with on the at least one ATM data output link at equally spaced time intervals, provided that there is at least one ATM cell contending for said at least one ATM data output link.

8. A switch as set forth in claim 1, the link list manager including a priority tournament resolution manager for evaluating the at least one ATM data output link for class of service priority at time intervals based on at least a counter value.

9. A switch for handling synchronous transfer mode digital data signals and asynchronous transfer mode digital data signals, comprising:

at least two data input links including at least one input link dedicated for handling synchronous data and at least one input link dedicated for handling asynchronous data;

at least two data output links including at least one output link dedicated for handling synchronous data and at least one output link dedicated for handling asynchronous data;

an input memory page coupled to the at least two data input links, the input memory page including at least two shift registers for accumulating and multiplexing bytes of input data;

a data buffer coupled to the input memory for storing bytes of multiplexed input data;

an output memory page coupled to the data buffer and the at least two data output links, the output memory page including at least two shift registers for accumulating and demultiplexing bytes of multiplexed data;

a link list manager control circuit for coordinating the flow of data into and out of the data buffer, the link list manager control circuit including a look-up memory including a link list logic table, a virtual path identifier/virtual channel identifier table, a link list memory and a routing table coupled to the data buffer for storing mapping instructions to the at least two data output links;

a write pointer for writing data from the input memory page into the data buffer; and

,

a read pointer for directing data values from the look-up memory to the output memory page.

10. A switch as set forth in claim 9 wherein the synchronous transfer mode digital data are switched by sending the synchronous transfer mode digital data from the at least one of the synchronous data input links to at least one output queue.

11. A switch as set forth in claim 9 wherein the asynchronous transfer mode digital signals are switched by channeling at least one asynchronous transfer mode cell from one of the at least two data input links to at least one output queue, the at least one output queue being associated with the at least one asynchronous data output link and a class of service.

12. A method of switching asynchronous transfer mode data and synchronous transfer mode data in a single switch comprising the steps of:

receiving one or more streams of synchronous data on one or more serial input links;

receiving one or more streams of asynchronous data cells on one or mo re serial input links;

accumulating bytes of asynchronous data from each of the asynchronous input links;

accumulating bytes of synchronous data from each of the synchronous input links, each byte of synchronous data being equal to the byte size and time frame duration of the asynchronous data cells;

converting the synchronous data bytes and asynchronous data bytes into parallel format and storing the parallel format data in an input memory;

routing each segment to a selected output link based on information contained in a routing table;

storing asynchronous transfer mode cells contending for the same output links in at least one asynchronous transfer mode data buffer;

reading data from the at least one asynchronous transfer mode data buffer into the selected output link;

wherein the step of storing asynchronous transfer mode segments contending for the same output links includes operating a pointer on a common pool of buffers according to a first-in-first-out link list associated with at least a class of service; and

,

wherein the requests from every class of service are serviced sequentially for as long as an associated counter and depth of an associated queue are not zero.

13. The method of claim 12 wherein each class of service is placed out of a priority tournament resolution manager when an associated counter has counted down to zero.

14. The method of claim 12 wherein one class of service request is serviced periodically, every time an associated counter matches an associated value, and when a service routine grants access to the output port immediately.