Method and apparatus for operating a PLL with a phase detector/sample hold circuit for synthesizing high-frequency signals for wireless communications

• US 6,167,245 A
• Filed: 05/29/1998
• Issued: 12/26/2000
• Est. Priority Date: 05/29/1998
• Status: Expired due to Term

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Wang, Caiyi, Welland, David R.
• Primary Examiner(s): Urban, Edward F.
• Assistant Examiner(s): Gesesse, Tilahun
• Application Number:
  US09/087,017
• Time in Patent Office: 942 Days
• Field of Search: 455/260, 455/165.1, 455/261, 455/265, 455/96, 455/75, 455/258, 455/255, 455/256, 331/36 C, 331/36 R, 331/177 V
• US Class Current: 455/260
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/187 using means for coarse tuning the voltage controlled oscillator of the loop H03L7/191 - H03L7/195 take precedence
• CPC Class Codes: H03L 7/199 with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers

Abstract

A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may include an analog control loop in which a phase detector circuit and sample and hold circuit are utilized. The output of the sample and hold circuit may be provided to the PLL VCO as VCO input control signals.

Claims

1. A method of operating a frequency synthesizer having a phase locked loop, comprising:

generating at least one first clock signal, the first clock signal being derived from an output clock signal of phase locked loop;

generating a second clock signal, the second clock signal being derived from a reference clock signal of phase locked loop;

detecting a phase difference between the at least one first clock signal and the second clock signal;

providing a phase difference output signal indicative of the detected phase difference;

sampling and holding the phase difference output signal at timed intervals;

generating at least one control signal from the sampling and holding step; and

controlling the output frequency of a controllable oscillator of the phase locked loop with the at least one control signal.

2. The method of claim 1,

the detecting a phase difference being performed with a phase detector having a plurality of first inputs, a second input, and at least a first output, the plurality of first inputs being coupled to an output of the controllable oscillator and the second input being coupled to the reference clock, the phase detector generating, a ramped analog output signal at the first output, the ramped analog output signal related to a phase difference between at least one of the first inputs and the second input;

and

the sampling and holding being performed with a sample and hold circuit coupled to the phase detector first output, the sample and hold circuit having at least one sample and hold output, the sample and hold output coupled to at least one input of the controllable oscillator.

3. The method of claim 2, wherein the plurality of first inputs are coupled to the controllable oscillator through a shift register and/or a clock divider.

4. The method of claim 2, the phase detector having a plurality of phase detector first outputs, the phase detector generating a plurality of ramped analog output signals.

5. The method of claim 4, wherein the sample and hold circuit has a plurality of outputs, and wherein the plurality of outputs are coupled to a plurality of inputs of the controllable oscillator.

6. The method of claim 2, wherein the sample and bold circuit has a plurality of outputs, and wherein the plurality of outputs are coupled to a plurality of inputs of the controllable oscillator.

7. The method of claim 6, wherein the controllable oscillator includes at least five inputs.

8. The method of claim 7, wherein the controllable oscillator includes at least twenty inputs.

9. The method of claim 2, further comprising a shift register coupled between the phase detector and the controllable oscillator output for generating one or more phase shifted signals.

10. The method of claim 2, the phase detector further comprising a ramped node, the ramped node being connected to a resistor.

11. The method of claim 1, the detecting a phase difference and providing a phase difference comprising:

generating a ramped analog signal indicative of the difference between the at least one first clock signal and the second clock signal.

12. The method of claim 11, further comprising generating a plurality of control signals for controlling the output frequency of the controllable oscillator, at least one control signal being generated by sampling the ramped analog signal.

13. The method of claim 12, a further comprising generating a plurality of ramped analog signals.

14. The method of claim 13, further comprising sampling each of the plurality of ramped analog signals, to generate the plurality of control signals.

15. The method of claim 14, wherein the plurality of control signals includes at least five control signals.

16. The method of claim 11, the at least one first clock signal being a frequency divided and phase shifted version of the output clock signal.

17. The method of operating a frequency synthesizer of claim 1, further comprising the steps of generating a plurality of control signals from the sampling and holding step and controlling the output frequency of the controllable oscillator of the phase locked loop with the plurality of control signals.

18. The method of operating a frequency synthesizer of claim 1, wherein the plurality of control signals is comprised of at least five signals.

19. The method of operating a frequency synthesizer of claim 1, wherein the plurality of control signals is comprised of at least twenty signals.

20. The method of operating a frequency synthesizer of claim 1, further comprising the steps of generating a plurality of first clock signals and detecting a phase difference between each of the plurality of first clock signals and the second clock signal.