Methods and apparatus for automatically generating interconnect patterns in programmable logic devices

• US 6,167,364 A
• Filed: 09/15/1998
• Issued: 12/26/2000
• Est. Priority Date: 04/17/1998
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Karchmer, David, Stellenberg, Daniel S.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Broda, Samuel
• Application Number:
  US09/153,754
• Time in Patent Office: 833 Days
• Field of Search: 703/13, 703/14, 703/15, 703/19, 703/20, 714/725, 716/4, 716/5, 716/6
• US Class Current: 703/19
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

Methods and apparatus are described for generating circuit parameters for a plurality of interconnect line circuit models. The plurality of circuit models represent a plurality of interconnect lines in a programmable logic device (PLD). Design description data corresponding to the PLD are generated at least in part from spreadsheet representations of the plurality of interconnect lines. A device model for the PLD is generated using estimated circuit parameters and a plurality of mathematical equations representing the plurality of interconnect line circuit models. Operation of the PLD is simulated using the device model and the design description data thereby generating modeled delay data corresponding to the estimated circuit parameters. The modeled delay data are compared with measured delay data corresponding to the plurality of interconnect lines. Where all of the modeled delay data are within an error limit of corresponding measured delay data, the estimated circuit parameters are designated as the circuit parameters.

Claims

1. A method for generating circuit parameters for a plurality of interconnect line circuit models, the plurality of circuit models representing a plurality of interconnect lines in a programmable logic device (PLD), the method comprising:

generating design description data corresponding to the PLD at least in part from interconnect line data representing the plurality of interconnect lines;

generating a device model for the PLD using estimated circuit parameters and a plurality of mathematical equations representing the plurality of interconnect line circuit models;

simulating operation of the PLD using the device model and the design description data thereby generating modeled delay data corresponding to the estimated circuit parameters;

comparing the modeled delay data with measured delay data corresponding to the plurality of interconnect lines; and

where all of the modeled delay data are within an error limit of corresponding measured delay data, designating the estimated circuit parameters as the circuit parameters.

2. The method of claim 1 wherein the interconnect line data comprise spreadsheet representations of the plurality of interconnect lines.

3. The method of claim 2 wherein generating design description data comprises generating a plurality of design description files corresponding to a hardware description of the PLD, the method further comprising:

compiling the design description files to generate the design description data; and

measuring actual delays for each of the plurality of interconnect lines in the PLD thereby generating the measured delay data.

4. The method of claim 2 wherein generating the device model comprises generating a device model file and wherein simulating operation of the PLD comprises compiling and simulating the device model file and the design description data.

5. The method of claim 2 further comprising:

generating a plurality of spreadsheets from the spreadsheet representations of the plurality of interconnect lines, each of the spreadsheets corresponding to one of the plurality of interconnect lines; and

incorporating the measured delay data and the modeled delay data into the plurality of spreadsheets;

wherein comparing the modeled delay data with the measured delay data comprises generating delta data representing differences between corresponding modeled and measured delay data.

6. The method of claim 5 wherein each of the plurality of spreadsheets comprises:

a pattern section representing the corresponding interconnect line;

a measured data section for recording the measured delay data;

a modeled delay data for recording the modeled delay data; and

a delta section for recording the delta data.

7. The method of claim 2 further comprising, where some of the modeled delay data are not within an error limit of corresponding measured delay data, manipulating selected ones of the estimated circuit parameters and repeating simulation of the operation of the PLD.

8. The method of claim 7 wherein manipulation of the estimated circuit parameters and simulation of the operation of the PLD are repeated until all of the modeled delay data are within the error limit of corresponding measured delay data.

9. The method of claim 2 wherein the spreadsheet representation of each interconnect line comprises a plurality of consecutive spreadsheet cells, each spreadsheet cell representing a connection point within the PLD for the corresponding interconnect line.

10. The method of claim 2 wherein selected ones of the plurality of interconnect line circuit models comprise a ladder network of resistors and capacitors.

11. The method of claim 10 wherein the selected interconnect line circuit models further comprise a plurality of load models coupled to the ladder network representing loads on the corresponding interconnect line in the PLD.

12. The method of claim 2 wherein generation of the device model employs adaptive simulated annealing (ASA).

13. The method of claim 12 further comprising:

generating C and H files using the estimated circuit parameters and the mathematical equations;

compiling the C and H files thereby generating an ASA solver executable;

running the ASA solver executable to generate first revised estimated circuit parameters;

revising the first revised estimated parameter using linear interpolation thereby generating second revised estimated circuit parameters; and

generating a device model file representing the device model using the second revised estimated circuit parameters.

14. The method of claim 2 wherein the estimated circuit parameters are designated as the circuit parameters only where all of the modeled delay data are greater than or equal to the corresponding measured delay data.

15. The method of claim 2 wherein the estimated circuit parameters are designated as the circuit parameters only where all of the modeled delay data are greater than or equal to the corresponding measured delay data plus a guardband value.

16. A computer program product for generating circuit parameters for a plurality of interconnect line circuit models, the plurality of circuit models representing a plurality of interconnect lines in a programmable logic device (PLD), the computer program product comprising:

at least one computer-readable medium; and

at least one computer program mechanism embedded in the at least one computer-readable medium for causing at least one computer to perform the steps of;

generating design description data corresponding to the PLD at least in part from spreadsheet representations of the plurality of interconnect lines;

generating a device model for the PLD using estimated circuit parameters and a plurality of mathematical equations representing the plurality of interconnect line circuit models;

simulating operation of the PLD using the device model and the design description data thereby generating modeled delay data corresponding to the estimated circuit parameters;

comparing the modeled delay data with measured delay data corresponding to the plurality of interconnect lines; and

where all of the modeled delay data are within an error limit of corresponding measured delay data, designating the estimated circuit parameters as the circuit parameters.

17. A programmable logic device (PLD) having a circuit design programmed therein, the circuit design having been simulated using a plurality of interconnect line circuit models representing a plurality of interconnect lines in the PLD, the interconnect line circuit models having circuit parameters associated therewith, the circuit parameters being generated according to a method comprising:

generating design description data corresponding to the PLD at least in part from spreadsheet representations of the plurality of interconnect lines;

generating a device model for the PLD using estimated circuit parameters and a plurality of mathematical equations representing the plurality of interconnect line circuit models;

simulating operation of the PLD using the device model and the design description data thereby generating modeled delay data corresponding to the estimated circuit parameters;

comparing the modeled delay data with measured delay data corresponding to the plurality of interconnect lines; and

where all of the modeled delay data are within an error limit of corresponding measured delay data, designating the estimated circuit parameters as the circuit parameters.

18. A method for verifying a circuit design for a programmable logic device comprising simulating the circuit design using a plurality of interconnect line circuit models representing a plurality of interconnect lines in the PLD, the interconnect line circuit models having circuit parameters associated therewith, the circuit parameters being generated according to a method comprising:

generating design description data corresponding to the PLD at least in part from spreadsheet representations of the plurality of interconnect lines;

generating a device model for the PLD using estimated circuit parameters and a plurality of mathematical equations representing the plurality of interconnect line circuit models;

simulating operation of the PLD using the device model and the design description data thereby generating modeled delay data corresponding to the estimated circuit parameters;

comparing the modeled delay data with measured delay data corresponding to the plurality of interconnect lines; and

where all of the modeled delay data are within an error limit of corresponding measured delay data, designating the estimated circuit parameters as the circuit parameters.

19. A method for generating circuit parameters for a plurality of interconnect line circuit models, the plurality of circuit models representing a plurality of interconnect lines in a programmable logic device (PLD), the method comprising:

1) generating design description files at least in part from spreadsheet representations of the plurality of interconnect lines, the design description files corresponding to a hardware representation of the PLD;

2) generating a plurality of spreadsheets from the spreadsheet representations, each of the spreadsheets corresponding to one of the plurality of interconnect lines;

3) measuring actual delays for each of the plurality of interconnect lines in the PLD thereby generating measured delay data;

4) generating a device model for the PLD using the spreadsheet representations, estimated circuit parameters, and a plurality of mathematical equations representing the plurality of interconnect line circuit models;

5) simulating operation of the PLD using the device model and the design description files thereby generating modeled delay data corresponding to the estimated circuit parameters;

6) incorporating the modeled delay data and the measured delay data into the plurality of spreadsheets thereby generating delta data representing differences between corresponding modeled and measured delay data;

8) where all of the modeled delay data are within an error limit of corresponding measured delay data, designating the preliminary interconnect parameters as the interconnect parameters; and

9) where at least some of the modeled delay data are not within the error limit, repeating steps (4)-(9).