Parallel access virtual channel memory system with cacheable channels

• US 6,167,486 A
• Filed: 11/18/1996
• Issued: 12/26/2000
• Est. Priority Date: 11/18/1996
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics America Inc.(f/k/a Integrated Device Technology, Inc) (Renesas Electronics Corporation)
• Original Assignee: NEC Electronics Incorporated (NEC Corporation)
• Inventors: Ando, Manabu, Lee, Jeffery H.
• Primary Examiner(s): PEIKARI, BEHZAD
• Application Number:
  US08/746,829
• Time in Patent Office: 1,499 Days
• Field of Search: 711/119, 711/5, 711/120, 711/123, 711/125, 711/126, 711/128, 711/137, 711/138, 711/145, 711/203, 711/204, 711/106, 711/148, 711/149, 711/150, 365/203, 365/222, 340/825.06, 395/855
• US Class Current: 711/120
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches

Abstract

A memory system having a main memory which is coupled to a plurality of parallel virtual access channels. Each of the virtual access channels provides a set of memory access resources for controlling the main memory. These memory access resources include cache resources (including cache chaining), burst mode operation control and precharge operation control. A plurality of the virtual access channels are cacheable virtual access channels, each of which includes a channel row cache memory for storing one or more cache entries and a channel row address register for storing corresponding cache address entries. One or more non-cacheable virtual access channels are provided by a bus bypass circuit. Each virtual access channel is addressable, such that particular memory masters can be assigned to access particular virtual access channels.

Claims

1. A memory system for connection to a system bus, the memory system comprising:

a memory bank bus;

a plurality of memory banks coupled to the memory bank bus;

a plurality of virtual access channels coupled in parallel between the system bus and the memory bank bus, wherein each of the virtual access channels provides a set of memory access resources for accessing any of the plurality of memory banks, and wherein each of the virtual access channels is independently addressable by signals provided on the system bus;

wherein the virtual access channels comprise one or more cacheable virtual access channels which perform caching operations; and

wherein each of the cacheable virtual access channels comprises a data cache memory and a corresponding address cache memory.

2. The memory system of claim 1, wherein each data cache memory comprises a plurality of cache entries, and each corresponding address cache memory comprises a corresponding plurality of cache address entries.

3. The memory system of claim 1, further comprising a virtual channel control circuit which enables the virtual access channels in response to signals received on the system bus.

4. The memory system of claim 1, further comprising means for prefetching data from the memory banks to a specified virtual access channel on the memory bank bus.

5. The memory system of claim 4, wherein the means for prefetching data concurrently implements prefetch operations in different ones of the memory banks.

6. The memory system of claim 4, wherein the means for prefetching data implements prefetch operations at the same time that data is transferred between the system bus and the virtual access channels.

7. The memory system of claim 1, further comprising means for restoring data stored in the virtual access channels to the memory banks.

8. A The memory system of claim 7, wherein the means for restoring data concurrently implements restore operations in different ones of the memory banks.

9. A The memory system of claim 7, wherein the means for restoring data implements restore operations at the same time that data is transferred between the system bus and the virtual access channels.

10. A memory system for connection to a system bus, the memory system comprising:

a memory bank bus;

a plurality of memory banks coupled to the memory bank bus;

a plurality of virtual access channels coupled in parallel between the system bus and the memory bank bus, wherein each of the virtual access channels provides a set of memory access resources for accessing any of the plurality of memory banks, and wherein each of the virtual access channels is independently addressable by signals provided on the system bus;

wherein the virtual access channels comprise one or more cacheable virtual access channels which perform caching operations; and

wherein the virtual access channels further comprise a non-cacheable virtual access channel which bypasses the cacheable virtual access channels.

11. A memory system for connection to a system bus, the memory system comprising:

a memory bank bus;

a plurality of memory banks coupled to the memory bank bus;

a plurality of virtual access channels coupled in parallel between the system bus and the memory bank bus, wherein each of the virtual access channels provides a set of memory access resources for accessing any of the plurality of memory banks, and wherein each of the virtual access channels is independently addressable by signals provided on the system bus;

wherein the virtual access channels comprise one or more cacheable virtual access channels which perform caching operations; and

a precharge control register which stores a plurality of precharge control bits, each precharge control bit corresponding to one of the cacheable virtual access channels, wherein each precharge control bit defines one of a plurality of precharge modes to be implemented by the corresponding cacheable virtual access channel.

12. A memory system for connection to a system bus, the memory system comprising:

a memory bank bus;

a plurality of memory banks coupled to the memory bank bus;

a plurality of virtual access channels coupled in parallel between the system bus and the memory bank bus, wherein each of the virtual access channels provides a set of memory access resources for accessing any of the plurality of memory banks, and wherein each of the virtual access channels is independently addressable by signals provided on the system bus;

wherein the virtual access channels comprise one or more cacheable virtual access channels which perform caching operations; and

a burst length control register which stores a plurality of burst length control bytes, each burst length control byte corresponding to one of the cacheable virtual access channels, wherein each burst length control byte defines a burst access length for the corresponding cacheable virtual access channel.

13. The memory system of claim 12, wherein the burst length control bytes are independently programmable to provide different cacheable virtual access channels with different burst access lengths.

14. A memory system for connection to a system bus, the memory system comprising:

a memory bank bus;

a plurality of memory banks coupled to the memory bank bus;

a plurality of virtual access channels coupled in parallel between the system bus and the memory bank bus, wherein each of the virtual access channels provides a set of memory access resources for accessing any of the plurality of memory banks, and wherein each of the virtual access channels is independently addressable by signals provided on the system bus;

wherein the virtual access channels comprise one or more cacheable virtual access channels which perform caching operations; and

a chain control register which stores a plurality of chain control bytes, wherein each chain control byte defines one of a plurality of chaining modes to be implemented within a corresponding cacheable virtual access channel.