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Parallel access virtual channel memory system with cacheable channels

  • US 6,167,486 A
  • Filed: 11/18/1996
  • Issued: 12/26/2000
  • Est. Priority Date: 11/18/1996
  • Status: Expired due to Fees
First Claim
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1. A memory system for connection to a system bus, the memory system comprising:

  • a memory bank bus;

    a plurality of memory banks coupled to the memory bank bus;

    a plurality of virtual access channels coupled in parallel between the system bus and the memory bank bus, wherein each of the virtual access channels provides a set of memory access resources for accessing any of the plurality of memory banks, and wherein each of the virtual access channels is independently addressable by signals provided on the system bus;

    wherein the virtual access channels comprise one or more cacheable virtual access channels which perform caching operations; and

    wherein each of the cacheable virtual access channels comprises a data cache memory and a corresponding address cache memory.

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