High performance digital electronic system architecture and memory circuit therefor

• US 6,167,491 A
• Filed: 03/05/1998
• Issued: 12/26/2000
• Est. Priority Date: 09/01/1994
• Status: Expired due to Fees

• Current Assignee: McAlpine, Gary L.
• Original Assignee: McAlpine, Gary L.
• Inventors: McAlpine, Gary L.
• Primary Examiner(s): Nguyen, Hiep T.
• Application Number:
  US09/035,640
• Time in Patent Office: 1,027 Days
• Field of Search: 711/131, 711/149, 711/168, 711/143, 711/146
• US Class Current: 711/149
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G11C 7/103 using serially addressed read-write data registers G11C7/1036 takes precedence

Abstract

A digital electronic system architecture having one or more system components and a memory coupled to selected system components, the memory selectively storing and communicating data among the coupled components. The digital electronic system preferably also has a transaction control bus, coupled to each of the selected system components and to the memory, for communicating command and control signals among the components and memory. A memory circuit is provided that has a plurality of ports, each of the ports (i) having an input terminal and an output terminal that transfer data independently of one another, (ii) operating independently of one another and (iii) being coupled respectively to one of the other system components for data communication therewith. A read interface for a memory array is provided that has a queue for receiving data read from a row of the array and a selection circuit for placing in the queue a contiguous block of the read data, the size of the block and its placement being selectable. The read interface preferably comprises a plurality of queues, and the selection circuit preferably is adapted to place independently selectable blocks of the read data in independently selectable positions in selected queues. A write interface for a memory array is also provided that has a queue for receiving data to be written to the array and a selection circuit for placing in the array a contiguous block of received data, the size of the block and its placement being selectable. The write interface preferably comprises a plurality of queues, and the selection circuit preferably is adapted to place independently selectable data received from selected queues in independently selectable positions in the memory array.

Claims

1. A digital electronic system enabling any of a plurality of components thereof to share a common main memory, said digital electronic system comprising:

a plurality of system components;

a common main memory having a plurality of data ports and a common address and control port;

a plurality of data circuits for interconnecting respective system components with corresponding data ports of said common main memory; and

a common address and control circuit for interconnecting said plurality of system components with said common address and control port of said common main memory, said common address and control circuit enabling said plurality of system components to access said common main memory, any of said plurality of system components being able to monitor said common address and control port for address and control information issued by any other of said plurality of system components.

2. The digital electronic system of claim 1, wherein said plurality of system components are capable of temporarily storing, in respective internal cache memories, copies of data retrieved from said common main memory, and are able to participate collectively in maintaining the coherency of multiple copies of said data in said cache memories and said common main memory.

3. The digital electronic system of claim 2, wherein said plurality of system components are able to monitor said common address and control circuit for address and control information issued by any other of said plurality of system components, said address and control information enabling a system component, holding in its respective cache memory a copy of the addressed data, to maintain the status and coherency of its copy of said addressed data.

4. The digital electronic system of claim 3, wherein the combination of said common address and control circuit, said plurality of data circuits, and said common main memory further enable a system component, temporarily storing in its cache memory a modified copy of said addressed data, to provide its copy of said addressed data for updating the corresponding copy in said common main memory and completing the transaction requested by said system component that referenced said addressed data.

5. The digital electronic system of claim 4, wherein said combination of common address and control circuit, said plurality of data circuits, and said common main memory further enable said system component that referenced said addressed data to receive said modified copy of said addressed data, said modified copy of said addressed data being routed through said common main memory from source system component to destination system component.

6. The digital electronic system of claim 1, wherein said plurality of system components are capable of exchanging data through said plurality of data circuits and said common main memory, any of said plurality of system components being able to monitor said common address and control circuit for address and control information issued by any other of said plurality of system components, said address and control information enabling one or more destination system components to determine that data transmitted to said common main memory by a source system component, in conjunction with said address and control information, is destined for said one or more destination system components.

7. The digital electronic system of claim 6, wherein said address and control information further enable said one or more destination system components to determine the address, in said common main memory, from which said data can be retrieved.

8. The digital electronic system of claim 6, wherein said address and control information further enable said one or more destination system components to receive data routed through said common main memory, from source system component to destination system component.

9. The digital electronic system of claim 6, wherein said address and control information further enable said source system component to determine the address, in said common main memory, from which said data was retrieved by said one or more destination system components.

10. The digital electronic system of claim 9, wherein said address and control information further enabling said source system component to determine when data was retrieved by each of said one or more destination system components.

11. A method for enabling any of a plurality of components of a digital electronic system to share a common main memory, comprising:

providing the common main memory with a plurality of data ports and a common address and control port; and

enabling said plurality of system components to access said common main memory so that any of said plurality of system components is able to monitor said common address and control port for address and control information issued by any other of said plurality of system components.

12. The method of claim 11, further comprising storing, in respective internal cache memories of said plurality of system components, copies of data retrieved from said common main memory, and causing said plurality of system components to participate collectively in maintaining the coherency of multiple copies of said data in said cache memories and said common main memory.

13. The method of claim 12, further comprising causing said plurality of system components to monitor said common address and control port for address and control information issued by any other of said plurality of system components so as to maintain the status and coherency of its copy of said addressed data.

14. The method of claim 13, further comprising enabling a system component, temporarily storing in its cache memory a modified copy of said addressed data, to provide its copy of said addressed data for updating the corresponding copy in said common main memory and completing the transaction requested by said system component that referenced said addressed data.

15. The method of claim 14, further comprising enabling said system component that referenced said addressed data to receive, through said common main memory, said modified copy of said addressed data.

16. The method of claim 11, further comprising enabling any of said plurality of system components to monitor said common address and control port for address and control information issued by any other of said plurality of system components, so as to determine that data transmitted to said common main memory by a source system component, in conjunction with said address and control information, is destined for one or more destination system components.

17. The method of claim 16, further comprising enabling said one or more destination system components to determine the address, in said common main memory, from which said data can be retrieved.

18. The method of claim 16, further comprising enabling said one or more destination system components to receive data routed through said common main memory, from source system component to destination system component.

19. The method of claim 16, further comprising enabling said source system component to determine the address, in said common main memory, from which said data was retrieved by said one or more destination system components.

20. The method of claim 19, further comprising enabling said source system component to determine when data was retrieved by each of said one or more destination system components.