Flip chip pre-assembly underfill process

• US 6,168,972 B1
• Filed: 12/22/1998
• Issued: 01/02/2001
• Est. Priority Date: 12/22/1998
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Zhou, Dashun S., Takahashi, Yasuhito, Wang, Wen-chou Vincent, Peters, Michael G.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): LEE, GRANVILL D
• Application Number:
  US09/218,781
• Time in Patent Office: 742 Days
• Field of Search: 438/108, 438/107, 438/106, 438/29, 438/156
• US Class Current: 438/108
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/06102 the bonding areas being at different heights
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/83102 using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/83191 wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83856 Pre-cured adhesive, i.e. B-stage adhesive
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01009 : Fluorine [F]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

An encapsulation process for flip-chip bonding chips to a substrate encapsulates solder balls on the chip in a separate encapsulation process in which the chip is coated with encapsulation layer and then a portion of the encapsulation layer is removed to expose a portion of the solder balls.

Claims

1. A method of forming an encapsulated array of solder bumps on a chip, the method comprising:

(a) patterning a set of solder bumps onto said chip;

(b) coating said solder bumps in a layer of an encapsulation material, said encapsulation material substantially covering said set of solder bumps on said chip;

(c) heating said encapsulation material at a sufficient temperature and for a sufficient length of time that said encapsulation material stiffens to a substantially non-pliable solid; and

(d) removing a portion of said layer of said encapsulation material to expose a conductive portion of each of said encapsulated solder bumps while the encapsulation material is on the chip.

2. A method of forming an encapsulated array of solder bumps on a first sample that may be bonded to another sample, the method comprising:

(a) patterning a set of solder bumps onto said first sample;

(b) coating said solder bumps in a layer of an encapsulation material comprising an epoxy material, said encapsulation material substantially covering said set of solder bumps on said first sample;

(c) heating said encapsulation material at a sufficient temperature and for a sufficient length of time that said encapsulation material stiffens to a substantially non-pliable solid which is hardened to a b-stage; and

(d) removing a portion of said layer of said b-stage encapsulation material to expose a conductive portion of each of said encapsulated solder bumps.

3. The method of claim 2, wherein said step (d) of removing a portion of the encapsulation material is performed by a chemical mechanical polishing process.

4. The method of claim 3, wherein said chemical mechanical polishing process removes about one half of each of said encapsulated solder bumps.

5. The method of claim 4, further comprising:

patterning solder pads on the polished surface of said chemically mechanically polished solder bumps.

6. The method of claim 5, wherein said patterned solder pads are formed using a solder ink.

7. The method of claim 5, wherein said solder pads are in the form of a deposited layer of solder.

8. The method of claim 2, wherein the solder bumps are solder balls.

9. A method of forming encapsulated solder joints in an array of solder joints formed between a chip and a substrate, comprising the steps of:

(a) patterning a first set of solder balls onto a first set of contact regions of the chip;

(b) coating the chip with a chip encapsulation material, said chip encapsulation material substantially covering said first set of solder balls disposed on said chip;

(c) removing a portion of said chip encapsulation material to expose a conductive surface portion of each of said first set of solder balls;

(d) patterning a second set of solder balls onto a second set of contact regions on the substrate;

(e) bringing said first set of solder balls on said chip into contact with said second set of solder balls on said substrate; and

(f) heating said chip and said substrate at a sufficient temperature for said first and second set of solder balls to reflow into solder joints.

10. The method of claim 9, wherein step (c) for removing a portion of the chip encapsulation material comprises the step of:

planarizing the encapsulated chip by using a chemical mechanical polishing process to polish the encapsulated chip to a common plane extending through a portion of said first set of solder balls.

11. The method of claim 10, further comprising the steps of:

coating the substrate with a substrate encapsulation material, said substrate encapsulation material substantially covering said second set of solder balls disposed on said substrate; and

removing a portion of said substrate encapsulation material to expose a conductive portion of each said second set of solder balls.

12. The method of claim 11, wherein said step for removing a portion of said substrate encapsulation material comprises the step of planarizing the encapsulated substrate by chemical mechanical polishing the encapsulated substrate to a common plane extending through a portion of said first set of solder balls.

13. The method of claim 12, wherein said substrate encapsulation material and said chip encapsulation material are composed of an epoxy that is heated to the b-stage and wherein the step (f) of heating said chip and said substrate is conducted at a sufficient temperature and with a sufficient pressure between said chip and said substrate so that said epoxy encapsulation layers are bonded together.

14. The method of claim 12, further including the step of patterning a solder pad over each said planarized second set of solder balls after said second set of solder balls are planarized.

15. A method of bonding a chip to a substrate, comprising the steps of:

(a) patterning a first set of solder balls onto a set of contact regions of the chip;

(b) coating the chip with a first layer of epoxy, said epoxy substantially covering said first set of solder balls disposed on said chip;

(c) heating said chip at a sufficient temperature for a sufficient time to convert said first layer of epoxy into a b-stage epoxy;

(d) planarizing said first layer of epoxy to reveal an exposed conductive surface portion of each said first set of solder balls;

(e) patterning a second set of solder balls onto a second set of contact regions on the substrate;

(f) coating the substrate with a second layer of epoxy, said epoxy substantially covering said second set of solder balls disposed on said substrate;

(g) heating said substrate at a sufficient temperature for a sufficient time to convert said second layer of epoxy into a b-stage epoxy;

(h) planarizing said second layer of epoxy to reveal a conductive surface portion of each said second set of solder balls;

(i) bringing said first set of solder balls on said chip into contact with said second set of solder balls on said substrate; and

(j) applying a sufficient pressure between said chip and said substrate at a sufficient temperature and for a sufficient time to bond said first layer of epoxy to said second layer of epoxy and reflowing said solder balls into solder joints.

16. The method of claim 15, further comprising the step of patterning a solder ink composed of flux, epoxy, and solder over one of said set of solder balls prior to the step of bring said solder balls on said chip and said substrate into contact with each other.

17. The method of claim 15, further comprising the step of patterning solder pads on said first or second set of solder balls after one said step of planarizing said surface.

18. The method of claim 15, further comprising the step of cleaning the surface of said epoxy layers prior to said step of bringing said solder balls on said chip and said substrate into contact.

19. The method of claim 18, wherein said cleaning step includes plasma etching.

20. The method of claim 19, wherein said cleaning step includes chemical etching.