Method of making a high-voltage transistor with multiple lateral conduction layers

• US 6,168,983 B1
• Filed: 02/05/1999
• Issued: 01/02/2001
• Est. Priority Date: 11/05/1996
• Status: Expired due to Term

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Disney, Donald R., Ajit, Janardhanan S., Rumennik, Vladimir
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): PHAM, HOAI V
• Application Number:
  US09/245,029
• Time in Patent Office: 697 Days
• Field of Search: 257/335-339, 257/341-343, 257/346, 257/141, 257/372, 257/345, 257/375, 257/376, 257/548-550, 438/301, 438/303, 438/305, 438/306, 438/299, 438/995, 438/140, 438/180, 438/188, 438/514, 438/519, 438/526, 438/527, 438/549, 438/199
• US Class Current: 438/188
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0852 of DMOS transistors
• CPC Class Codes: H01L 29/0873 Drain regions
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A method for making a high voltage insulated gate field-effect transistor having an insulated gate field-effect device structure with a source and a drain comprises the steps of forming the drain with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. A minimal number of processing steps are required to form the parallel JFET conduction channels which provide the HVFET with a low on-state resistance.

Claims

1. A method of fabricating an extended drain of a high-voltage field-effect transistor (HVFET) comprising:

(a) forming a well region of a first conductivity type in a substrate of a second conductivity type, the well region having a laterally extended portion;

(b) implanting a dopant of the second conductivity type into the laterally extended portion of the well region to form a buried region therein, the implant being performed through a masking layer having a varying thickness formed over the substrate such that the buried region comprises buried sections disposed at different depths within the well region;

(c) forming a drain diffusion region of the first conductivity type in the well.

2. The method according to claim 1 wherein the buried region is disposed beneath a surface of the substrate.

3. The method according to claim 1, wherein step (a) comprises:

implanting a dopant of the first conductivity type into the substrate;

diffusing the dopant in the substrate.

4. The method according to claim 1 wherein the first conductivity type is n-type and the second conductivity type is p-type.

5. The method according to claim 1 wherein the drain diffusion region is spaced-apart from the buried region.

6. The method according to claim 1 wherein the masking layer has a discontinuous thickness.

7. A method of fabricating an extended drain of a high-voltage field-effect transistor (HVFET) comprising:

(a) forming a well region of a first conductivity type in a substrate of a second conductivity type, the well region having a laterally extended portion;

(b) implanting a first dopant of the second conductivity type into the laterally extended portion of the well region to form a first buried region therein;

(c) implanting a second dopant of the second conductivity type into the laterally extended portion of the well region to form a second buried region therein, the second buried region being disposed at a different depth in the well region than the first buried region such that a JFET conduction channel is formed between the first and second buried regions; and

(d) forming a drain diffusion region of the first conductivity type in the well.

8. The method according to claim 7 wherein the first buried region is disposed approximately 0.5-2.0 μ

m beneath a surface of the substrate.

9. The method according to claim 7, wherein the first dopant is the same as the second dopant.

10. The method according to claim 7 wherein the first conductivity type is n-type and the second conductivity type is p-type.

11. The method according to claim 7 wherein the drain diffusion region is spaced-apart from both the first and second buried regions.

12. The method according to claim 7 wherein the first buried region is disposed above the second buried region.

13. A method of fabricating a high-voltage field-effect transistor (HVFET) comprising:

(a) forming a well region of a first conductivity type in a substrate of a second conductivity type, the well region having a laterally extended portion with a lateral boundary;

(b) implanting a dopant of the second conductivity type into the substrate to form a first buried region within the laterally extended portion of the well region and a second buried region in the substrate, the first buried region being disposed beneath a surface of the substrate such that dual JFET conduction channels are formed above and below the first buried region;

(c) forming a gate insulated from the substrate by a gate oxide layer, the gate extending over the substrate adjacent the well region;

(d) implanting a dopant of the first conductivity type into the substrate to form a source diffusion region spaced-apart from the well region and above the second buried region, the dopant also being implanted into the well region to form a drain diffusion region spaced-apart from the first buried region, a channel region being formed between the source diffusion region and the well region under the gate; and

(e) forming source and drain electrodes connected to the source and drain diffusion regions, respectively.

14. The method according to claim 13 wherein step (b) is performed through a masking layer having a discontinuous thickness such that the first buried region comprises separate buried layer sections disposed at different depths within the well region.

15. The method according to claim 14 wherein the masking layer comprises an oxide.

16. The method according to claim 13 wherein the first buried region is disposed approximately 0.5-2.0 μ

m beneath a surface of the substrate.

17. The method according to claim 13 wherein the first conductivity type is n-type and the second conductivity type is p-type.

18. The method according to claim 13 wherein the second buried layer is spaced-apart from the lateral boundary by a region of the substrate beneath the channel region.

19. The method according to claim 13 wherein the first buried region is spaced-apart from the lateral boundary.

20. A method of fabricating a high-voltage field-effect transistor (HVFET) comprising:

(a) forming a well region of a first conductivity type in a substrate of a second conductivity type, the well region having a laterally extended portion with a lateral boundary;

(b) successively implanting a dopant of the second conductivity type into the substrate to form a plurality of buried layers within the laterally extended portion of the well region, each successive implant being performed at a different energy such that the plurality of buried layers are spaced-apart from one another thereby creating an associated plurality of JFET conduction channels within the well region;

(c) forming a gate insulated from the substrate by a gate oxide layer, the gate extending over the substrate adjacent the well region;

(d) forming a source diffusion region in the substrate spaced-apart from the well region, a channel region being formed between the source diffusion region and the well region under the gate; and

(e) forming a drain diffusion region in the well region.

21. The method according to claim 20 further comprising:

(f) forming source and drain electrodes connected to the source and drain diffusion regions, respectively.

22. The method according to claim 20 wherein an uppermost one of the plurality of buried layers is contiguous with a surface of the substrate.

23. The method according to claim 20 wherein an uppermost one of the plurality of buried layers is disposed beneath a surface of the substrate.

24. The method according to claim 23 wherein the uppermost one of the plurality of buried layers is disposed approximately 0.5-2.0 μ

m below a surface of the substrate.

25. The method according to claim 20 wherein the first conductivity type is n-type and the second conductivity type is p-type.

26. The method according to claim 20 wherein each of the plurality of buried layers is spaced-apart from the lateral boundary of the well region.

27. The method according to claim 20 wherein step (b) also forms a corresponding plurality of additional buried layers in an area of the substrate that is beneath the source diffusion region.

28. The method according to claim 20 wherein step (b) is performed through a masking layer having a discontinuous thickness such that a first buried layer comprises separate buried sections disposed at different depths within the well region.

29. The method according to claim 28 wherein the masking layer comprises an oxide.

30. A method of fabricating an extended drain of a high-voltage field-effect transistor (HVFET) comprising:

(a) forming a well region of a first conductivity type in a substrate of a second conductivity type, the well region having a laterally extended portion;

(b) forming a masking layer over the laterally extended portion of the well region, the masking layer having a varying thickness; and

(c) implanting a dopant of the second conductivity type through the masking layer to form a buried region within the well region, the buried region comprising separate buried sections disposed at different depths within the well region corresponding to the varying thickness of the masking layer.

31. A method of fabricating an extended drain of a high-voltage field-effect transistor (HVFET) comprising:

(a) forming a drain diffusion region of a first conductivity type in a semiconductor material of a second conductivity type;

(b) successively implanting a dopant of the second conductivity type into the semiconductor material to form a plurality of buried layers along with an associated plurality of parallel-configured JFET conduction channels each of which is formed at a different depth below a surface of the semiconductor material, the JFET conduction channels being connected to, and extending laterally from, the drain diffusion region.

32. The method according to claim 31 wherein an uppermost one of the JFET conduction channels is disposed beneath the surface of the semiconductor material.

33. The method according to claim 31 wherein the semiconductor material comprises an epitaxial layer formed over a substrate.

34. The method according to claim 31 wherein the semiconductor material comprises a substrate.

35. The method according to claim 32 wherein the uppermost one of the JFET conduction channels is disposed approximately 0.5-2.0 μ

m below a surface of the semiconductor material.

36. The method according to claim 31 wherein the first conductivity type is n-type and the second conductivity type is p-type.

37. The method according to claim 31 further comprising:

forming a drain electrode connected to the drain diffusion region.

38. A method of fabricating a high-voltage field-effect transistor (HVFET) comprising:

forming an epitaxial layer of a first conductivity type over a substrate of a second conductivity type;

forming a first region of the second conductivity type in the epitaxial layer, the first region having a boundary;

forming an insulated gate over a portion of the first region;

forming a source diffusion region in the first region a channel region being defined in an area of the first region between the source diffusion region and the boundary, the insulated gate being disposed over the channel region;

implanting a dopant into the epitaxial layer to form a buried region of the second conductivity type disposed therein, the buried region being disposed beneath a top surface of the epitaxial layer such that dual JFET conduction channels are formed above and below the buried region; and

forming a drain diffusion region in the epitaxial layer spaced-apart from the buried region.

39. The method according to claim 38 wherein the buried region is spaced-apart from the channel region.

40. The method according to claim 38 wherein the implanting step is performed through a masking layer having a discontinuous thickness such that the buried region comprises separate buried sections disposed at different depths within the epitaxial layer.

41. The method according to claim 38 wherein the masking layer comprises an oxide.

42. The method according to claim 38 further comprising:

forming an isolation region connected to the substrate and the first region.

43. The method according to claim 38 wherein the first conductivity type is n-type and the second conductivity type is p-type.

44. The method according to claim 38 wherein the buried region comprises a plurality of buried layers disposed at different depths within the epitaxial layer.

45. The method according to claim 38 wherein the implanting step also forms an additional buried region underneath the source diffusion region.