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Method of making a high-voltage transistor with multiple lateral conduction layers

  • US 6,168,983 B1
  • Filed: 02/05/1999
  • Issued: 01/02/2001
  • Est. Priority Date: 11/05/1996
  • Status: Expired due to Term
First Claim
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1. A method of fabricating an extended drain of a high-voltage field-effect transistor (HVFET) comprising:

  • (a) forming a well region of a first conductivity type in a substrate of a second conductivity type, the well region having a laterally extended portion;

    (b) implanting a dopant of the second conductivity type into the laterally extended portion of the well region to form a buried region therein, the implant being performed through a masking layer having a varying thickness formed over the substrate such that the buried region comprises buried sections disposed at different depths within the well region;

    (c) forming a drain diffusion region of the first conductivity type in the well.

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