Semiconductor integrated circuit having an input and output protective circuit

• US 6,169,311 B1
• Filed: 10/27/1998
• Issued: 01/02/2001
• Est. Priority Date: 10/27/1997
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Iwasaki, Tadashi
• Primary Examiner(s): HARDY, DAVID B
• Application Number:
  US09/179,412
• Time in Patent Office: 798 Days
• Field of Search: 257/357, 257/358, 361/90, 361/91, 361/92
• US Class Current: 257/358
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/0288 using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps

Abstract

Disclosed is a MOS-type semiconductor integrated circuit, which has: an input circuit section connected to an input pad; an output circuit section connected to an output pat; and an internal circuit section connected between the input circuit section and the output circuit section; wherein the input circuit section includes a first n-channel transistor, a first p-channel transistor and a first protective resistance connected between the first n-channel transistor and the first p-channel transistor, the input pad being connected between the first p-channel transistor and the first protective resistance, the internal circuit section being connected between the first n-channel transistor and the first protective resistance; and the output circuit section includes a second nchannel transistor, a second p-channel transistor and a second protective resistance connected between the second n-channel transistor and the second p-channel transistor, the output pad being connected between the second p-channel transistor and the second protective resistance, the internal circuit section being connected to the second n-channel transistor and the second p-channel transistor.

Claims

1. A MOS-type semiconductor integrated circuit, comprising:

an input circuit section including an n-channel transistor, a p-channel transistor and a protective resistance connected between said n-channel transistor and said p-channel transistor;

wherein an input part is connected between said p-channel transistor and said protective resistance and an output part is connected between said n-channel transistor and said protective resistance.

2. A semiconductor integrated circuit, according to claim 1, wherein:

said p-channel transistor is connected between said input part and a power source line and said n-channel transistor is connected between said protective resistance and a ground line.

3. A semiconductor integrated circuit, according to claim 2, wherein:

said protective resistance is formed in a well region in a semiconductor substrate where a silicide layer of diffusion layer region is separated by a gate electrode formed on said semiconductor substrate.

4. A semiconductor integrated circuit, according to claim 2, wherein:

said protective resistance is formed in a well region in a semiconductor substrate where a silicide layer of diffusion layer region is separated by a LOCOS region formed on said semiconductor substrate.

5. A semiconductor integrated circuit, according to claim 1, wherein:

said protective resistance is formed in a well region in a semiconductor substrate where a silicide layer of diffusion layer region is separated by a gate electrode formed on said semiconductor substrate.

18. A semiconductor integrated circuit, according to claim 1, wherein:

said protective resistance is formed in a well region in a semiconductor substrate where a silicide layer of diffusion layer region is separated by a LOCOS region formed on said semiconductor substrate.

6. A MOS-type semiconductor integrated circuit, comprising:

an input circuit section connected to an input pad;

an output circuit section connected to an output pad; and

an internal circuit section connected between said input circuit section and said output circuit section;

wherein said input circuit section includes a first n-channel transistor, a first p-channel transistor and a first protective resistance connected between said first n-channel transistor and said first p-channel transistor, said input pad being connected between said first p-channel transistor and said first protective resistance, said internal circuit section being connected between said first n-channel transistor and said first protective resistance; and

said output circuit section includes a second n-channel transistor, a second p-channel transistor and a second protective resistance connected between said second n-channel transistor and said second p-channel transistor, said output pad being connected between said second p-channel transistor and said second protective resistance, said internal circuit section being connected to said second n-channel transistor and said second p-channel transistor.

7. A semiconductor integrated circuit, according to claim 6, wherein:

said protective resistance is formed in a well region in a semiconductor substrate where a silicide layer of diffusion layer region is separated by a LOCOS region formed on said semiconductor substrate.

8. A semiconductor integrated circuit, according to claim 6, wherein:

said first and second p-channel transistors and said internal circuit section are connected to a power source line; and

said first and second n-channel transistors and said internal circuit section are connected to a ground line.

9. A semiconductor integrated circuit, according to claim 8, wherein:

said input circuit section is connected to the gate electrode of a transistor in said internal circuit section.

10. A semiconductor integrated circuit, according to claim 9, wherein:

said protective resistance is formed in a well region in a semiconductor substrate where a silicide layer of diffusion layer region is separated by a gate electrode formed on said semiconductor substrate.

11. A semiconductor integrated circuit, according to claim 9, wherein:

said protective resistance is formed in a well region in a semiconductor substrate where a silicide layer of diffusion layer region is separated by a LOCOS region formed on said semiconductor substrate.

12. A semiconductor integrated circuit, according to claim 8, wherein:

said protective resistance is formed in a well region in a semiconductor substrate where a silicide layer of diffusion layer region is separated by a gate electrode formed on said semiconductor substrate.

13. A semiconductor integrated circuit, according to claim 8, wherein:

said protective resistance is formed in a well region in a semiconductor substrate where a silicide layer of diffusion layer region is separated by a LOCOS region formed on said semiconductor substrate.

14. A semiconductor integrated circuit, according to claim 6, wherein:

said input circuit section is connected to the gate electrode of a transistor in said internal circuit section.

15. A semiconductor integrated circuit, according to claim 14, wherein:

said protective resistance is formed in a well region in a semiconductor substrate where a silicide layer of diffusion layer region is separated by a gate electrode formed on said semiconductor substrate.

16. A semiconductor integrated circuit, according to claim 14, wherein:

said protective resistance is formed in a well region in a semiconductor substrate where a silicide layer of diffusion layer region is separated by a LOCOS region formed on said semiconductor substrate.

17. A semiconductor integrated circuit, according to claim 7, wherein:

said protective resistance is formed in a well region in a semiconductor substrate where a silicide layer of diffusion layer region is separated by a gate electrode formed on said semiconductor substrate.