Metal oxide semiconductor field effect transistor (MOSFET) and method for making thereof

• US 6,169,315 B1
• Filed: 02/18/1998
• Issued: 01/02/2001
• Est. Priority Date: 12/28/1995
• Status: Expired due to Fees

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Son, Jeong-Hwan
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Nadav, Ori
• Application Number:
  US09/025,504
• Time in Patent Office: 1,049 Days
• Field of Search: 257/344, 257/408, 257/401, 257/406, 438/177, 438/182, 438/193, 438/195, 438/595, 438/596
• US Class Current: 257/408
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66492 with a pocket or a lightly doped drain selectively formed at the side of the gate
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
• CPC Class Codes: H01L 29/7836 with a significant overlap between the lightly doped extension and the gate electrode H01L29/7834, H01L29/7835 take precedence

Abstract

A metal oxide semiconductor field effect transistor includes source and drain regions formed between a gate. The gate comprises a first conductive layer and a second conductive layer formed on the first conductive layer, and the second conductive layer has curved sidewalls with an insulating layer formed adjacent to the sidewalls. The method of making such a transistor improves the fabrication process, since the deposition thickness is controlled rather than the amount of etching. The transistor has a shortened channel width with reduced overlap capacitance, and the LDD doping compensation phenomenon is removed.

Claims

1. A semiconductor device, comprising:

a substrate;

a channel region in said substrate;

a gate insulation layer formed on said channel region;

a gate formed on said gate insulation layer, wherein said gate comprises,

a first conductive layer on the gate insulation layer that has a width extending in a first direction along the gate insulation layer that determines the prescribed width of the gate, wherein the first conductive layer includes vertical portions extending from outer end portions in a second direction substantially perpendicular to the first direction away from the gate insulation layer, and wherein the vertical portions have first sidewalls,

a second conductive layer formed on an upper surface of said first conductive layer with curved second sidewalls that taper from a narrower bottom portion of the second conductive layer to a wider top portion as distance from the first conductive layer increases in the second direction, wherein the second sidewalls oppose the first sidewalls and

an insulating layer formed between and adjacent to both the curved sidewalls and the first sidewalls;

source and drain regions formed on opposite sides of said gate; and

two lightly doped source and drain regions beneath said first conductive layer of said gate respectively adjacent the source and the drain with said channel region therebetween, wherein the two lightly doped source and drain regions are below the insulating layer, and wherein a width of the narrower bottom portion of the second conductive region determines a width of the channel region.

2. The semiconductor device of claim 1, wherein the width of the channel region is not determined by a widest portion of the second conductive layer.

3. The semiconductor device of claim 1, wherein said first conductive layer has a thinner thickness than said second conductive layer and has a width larger than said second conductive layer.

4. The semiconductor device of claim 1, further comprising a punch-through stop region formed beneath said channel region, wherein the second conductive layer has curved sidewalls.

5. The semiconductor device of claim 1, wherein the first conductive layer extends on the gate insulation layer between outer side ends, and wherein each of the lightly doped source and drain regions extend below a bottom surface of the second conductive layer having the lower width and below the vertical portions of the first conductive layer, and wherein each of the source and drain regions extends below the vertical portions of the first conductive layer.

6. A semiconductor device, comprising:

a substrate;

a channel region in said substrate;

a gate insulation layer on said channel region;

a gate having a prescribed width on said gate insulation layer, wherein said gate comprises,

a first conductive layer on the gate insulation layer that has a width extending in a first direction along the gate insulation layer that determines the prescribed width of the gate, wherein the first conductive layer includes vertical portions extending from outer end portions in a second direction substantially perpendicular to the first direction away from the gate insulation layer, and wherein the vertical portions have first sidewalls,

a second conductive layer on said first conductive layer, said second conductive layer having second sidewalls opposing the first sidewalls, wherein the second conductive layer increases in width in the second direction as distance from the gate insulation layer increases to have a wider top portion and a narrower bottom portion so that the second sidewalls taper, wherein a width of the narrower bottom portion determines a width of the channel region, and

an insulating layer formed between the first and second sidewalls; and

two lightly doped source and drain regions beneath said first conductive layer of said gate and beneath the insulating layer with said channel region therebetween.

7. The semiconductor device of claim 6, wherein the two lightly doped source and drain regions beneath the first conductive layer are between the first and second sidewalls.

8. The semiconductor device of claim 6, further comprising:

source and drain regions formed on oppose sides of said gate; and

a punch-through stop region formed beneath said channel region.

9. The semiconductor device of claim 8, wherein each of the lightly doped source and drain regions extend below a bottom surface of the second conductive layer at the narrower bottom portion and below the vertical portions of the first conductive layer, and wherein each of the source and drain regions extends below the vertical portions of the first conductive layer.