Programming architecture for field programmable gate array

• US 6,169,416 B1
• Filed: 09/01/1998
• Issued: 01/02/2001
• Est. Priority Date: 09/01/1998
• Status: Expired due to Term

• Current Assignee: QuickLogic Corporation
• Original Assignee: QuickLogic Corporation
• Inventors: Kolze, Paige A., Eaton, David D.
• Primary Examiner(s): SANTAMAURO, JON P
• Application Number:
  US09/145,581
• Time in Patent Office: 854 Days
• Field of Search: 326/37-39, 327/525
• US Class Current: 326/38
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

The programmable logic of a programmable device is sectioned into four logic regions. Each logic region includes logic elements and a programmable interconnect structure employing antifuses for programmably interconnecting selected ones of those logic elements. Programming conductors for supplying programming current to antifuses of a logic region extend across the logic region but do not extend across other logic regions. Similarly, programming control conductors that control programming transistors of the logic region extend across the logic region but do not extend across other logic regions. The programmable device structure allows four antifuses to be programmed simultaneously, one antifuse in each logic region. An antifuse can be selected for simultaneous programming from a logic region, irrespective of the other three antifuses that are or may be selected for simultaneous programming from the other three logic regions. Four programming current multiplexers and four programming buses are provided for each logic region so that the programming current that programs each antifuse flows from a separate input terminal. The resistance of the programming conductors is reduced by the use of parallel strips of metal in multiple metal layers.

Claims

1. An integrated circuit, comprising:

a first logic region and a second logic region disposed in a row, the row extending in a first dimension, the first logic region comprising a first programming transistor, a first routing conductor, a first antifuse, a second programming transistor, and a second routing conductor, the second logic region comprising a third programming transistor, a third routing conductor, a second antifuse, a fourth routing conductor, and a fourth programming transistor;

a first programming conductor extending in the first dimension across the first logic region and toward the second logic region, the first programming conductor being coupled to the first programming transistor, the first programming conductor not being coupled to any programming transistor in the second logic region;

a second programming conductor extending parallel to the first programming conductor in the first dimension across the first logic region and toward the second logic region, the second programming conductor being coupled to the second programming transistor, the second programming conductor not being coupled to any programming transistor in the second logic region, the first antifuse being programmable by conducting a programming current through the first programming conductor, through the first programming transistor, through the first routing conductor, through the first antifuse, through the second routing conductor, through the second programming transistor, and through the second programming conductor to couple the first routing conductor to the second routing conductor;

a third programming conductor extending in the first dimension across the second logic region and toward the first logic region, the third programming conductor being coupled to the third programming transistor, the third programming conductor not being coupled to any programming transistor in the first logic region; and

a fourth programming conductor extending parallel to the third programming conductor in the first dimension across the second logic region and toward the first logic region, the fourth programming conductor being coupled to the fourth programming transistor, the fourth programming conductor not being coupled to any programming transistor in the first logic region, the second antifuse being programmable by conducting a programming current through the third programming conductor, through the third programming transistor, through the third routing conductor, through the second antifuse, through the fourth routing conductor, through the fourth programming transistor, and through the fourth programming conductor to couple the third routing conductor to the fourth routing conductor.

2. The integrated circuit of claim 1, wherein the first programming conductor is collinear with the third programming conductor, the second programming conductor being collinear with the fourth programming conductor.

3. The integrated circuit of claim 1, wherein the first logic region has a rectangular shape with four sides, the second logic region having four sides and having the same rectangular shape that the first logic region has, a first side of the first logic region extending in the first dimension and being collinear with a first side of the second logic region, a second side of the first logic region extending in the first dimension and being collinear with a second side of the second logic region.

4. The integrated circuit of claim 3, wherein the first programming conductor does not extend across the second logic region, the second programming conductor does not extend across the second logic region, the third programming conductor does not extend across the first logic region, and the fourth programming conductor does not extend across the first logic region.

5. The integrated circuit of claim 3, further comprising:

a first programming control conductor extending in a second dimension perpendicular to the first dimension, the first and second programming transistors having gate electrodes, the first programming control conductor being coupled to the gate electrodes of the first and second programming transistors; and

a second programming control conductor extending in the second dimension parallel to the first programming control conductor, the third and fourth programming transistors having gate electrodes, the second programming control conductor being coupled to the gate electrodes of the third and fourth programming transistors.

6. The integrated circuit of claim 1, further comprising:

a first programming bus;

a first programming current multiplexer having a first input lead, a second input lead, a select input lead, and an output lead coupled to the first programming bus;

a first programming driver having an input lead coupled to the first programming bus and an output lead coupled to the first programming conductor;

a second programming bus;

a second programming current multiplexer having a first input lead, a second input lead, a select input lead, and an output lead coupled to the second programming bus;

a second programming driver having an input lead coupled to the second programming bus and an output lead coupled to the second programming conductor;

a third programming bus;

a third programming current multiplexer having a first input lead, a second input lead, a select input lead, and an output lead coupled to the third programming bus;

a third programming driver having an input lead coupled to the third programming bus and an output lead coupled to the third programming conductor;

a fourth programming bus;

a fourth programming current multiplexer having a first input lead, a second input lead, a select input lead, and an output lead coupled to the fourth programming bus; and

a fourth programming driver having an input lead coupled to the fourth programming bus and an output lead coupled to the fourth programming conductor.

7. The integrated circuit of claim 6, further comprising:

a first programming current terminal coupled to the first input lead of the first programming current multiplexer and to the first input lead of the second programming current multiplexer;

a second programming current terminal coupled to the second input lead of the first programming current multiplexer and to the second input lead of the second programming current multiplexer;

a third programming current terminal coupled to the first input lead of the third programming current multiplexer and to the first input lead of the fourth programming current multiplexer; and

a fourth programming current terminal coupled to the second input lead of the third programming current multiplexer and to the second input lead of the fourth programming current multiplexer.

8. The integrated circuit of claim 7, wherein the first programming current terminal is a ground terminal.

9. The integrated circuit of claim 6, further comprising:

a first plurality of programming drivers disposed in a column extending in the second dimension, the first and second programming drivers being ones of the first plurality of programming drivers; and

a second plurality of programming drivers disposed in a column extending in the second dimension, the third and fourth programming drivers being ones of the second plurality of programming drivers.

10. The integrated circuit of claim 1, wherein the first programming conductor extends over the first routing conductor, the second programming conductor extends over the second routing conductor, the third programming conductor extends over the third routing conductor, and the fourth programming conductor extends over the fourth routing conductor.

11. The integrated circuit of claim 1, wherein the first programming conductor extends under the first routing conductor, the second programming conductor extends under the second routing conductor, the third programming conductor extends under the third routing conductor, and the fourth programming conductor extends under the fourth routing conductor.

12. The integrated circuit of claim 1, wherein the integrated circuit is a field programmable gate array, wherein the first logic region comprises a plurality of logic cells and a programmable interconnect structure, the first routing conductor, the first antifuse, and the second routing conductor being part of the programmable interconnect structure of the first logic region, and wherein the second logic region comprises a plurality of logic cells and a programmable interconnect structure, the third routing conductor, the second antifuse, and the fourth routing conductor being part of the programmable interconnect structure of the second logic region.

13. The integrated circuit of claim 1, wherein the integrated circuit comprises a first layer of metal and a second layer of metal, an intermetal layer insulator being disposed between the first layer of metal and the second layer of metal, wherein the first programming conductor comprises a strip of metal of said first layer of metal and a strip of metal of said second layer of metal, said strip of metal of said first layer and said strip of metal of said second layer extending in parallel to one another, said first programming conductor further comprising a plurality of conductive plugs disposed along said first programming conductor to couple said strip of metal of said first layer to said strip of metal of said second layer through said intermetal layer insulator at a plurality of locations along said programming conductor.

14. The integrated circuit of claim 13, wherein there are more than three of said plurality of conductive plugs.

15. A method of simultaneously programming four antifuses of a field programmable gate array (FPGA), the FPGA having four logic regions, the method comprising:

conducting a first programming current from a first terminal of the integrated circuit, through a first programming current multiplexer, through a first programming conductor, through a first of the four antifuses, through a second programming conductor, through a second programming current multiplexer, and to a second terminal of the integrated circuit, wherein the first of the four antifuses is disposed in a first of the four logic regions, and neither the first nor the second programming conductor extend into a second, a third, or a fourth of the logic regions;

conducting a second programming current from a third terminal of the integrated circuit, through a third programming current multiplexer, through a third programming conductor, through a second of the four antifuses, through a fourth programming conductor, through a fourth programming current multiplexer, and to the second terminal of the integrated circuit, wherein the second of the four antifuses is disposed in the second of the four logic regions, and neither the third nor the fourth programming conductor extend into the first, third, or fourth of the logic regions;

conducting a third programming current from a fourth terminal of the integrated circuit, through a fifth programming current multiplexer, through a fifth programming conductor, through a third of the four antifuses, though a sixth programming conductor, through a sixth programming current multiplexer, and to the second terminal of the integrated circuit, wherein the third of the four antifuses is disposed in the third of the four logic regions, and neither the fifth nor the sixth programming conductor extend into the first, second, or fourth of the logic regions; and

conducting a fourth programming current from a fifth terminal of the integrated circuit, through a seventh programming current multiplexer, through a seventh programming conductor, through a fourth of the four antifuses, through an eighth programming conductor, through an eighth programming current multiplexer, and to the second terminal of the integrated circuit, wherein the fourth of the four antifuses is disposed in the fourth of the four logic regions, and neither the seventh nor the eighth programming conductor extend into the second, third, or fourth of the logic regions.

16. The method of claim 15, wherein the second terminal is a ground terminal.

17. The method of claim 15, wherein the first and second programming, conductor extend parallel to each other.

18. The method of claim 15, wherein the first and second programming conductors extend perpendicularly to each other.

19. An integrated circuit, comprising:

a logic array having a first logic region, a second logic region, a third logic region, and a fourth logic region; and

means for simultaneously programming any one first antifuse in the first logic region at the same time that a second antifuse is programmed in the second logic region, a third antifuse is programmed in the third logic region, and a fourth antifuse is programmed in the fourth logic region;

wherein the means also supply a first programming current to the first antifuse from a first programming current terminal, a second programming current to the second antifuse from a second programming current terminal, a third programming current to the third antifuse from a third programming current terminal, and a fourth programming current to the fourth antifuse from a fourth programming current terminal; and

wherein the first programming current does not flow through the second, third, or fourth logic regions, the second programming current does not flow through the first, third, or fourth logic regions, the third programming current does not flow through the first, second, or fourth logic regions, and the fourth programming current does not flow through the first, second, or third logic regions.

20. The integrated circuit of claim 19, wherein the means comprises:

a first set of four programming buses and four programming current multiplexers associated with the first logic region;

a second set of four programming buses and four programming current multiplexers associated with the second logic region;

a third set of four programming buses and four programming current multiplexers associated with the third logic region; and

a fourth set of four programming buses and four programming current multiplexers associated with the fourth logic region.

21. The integrated circuit of claim 19, wherein the first logic region and the second logic region are disposed in a row that extends in a first dimension, and wherein the first logic region and the third logic region are disposed in a column that extends in a second dimension perpendicular to the first dimension, wherein an axis extending in the first dimension intersects both the first antifuse and the second antifuse.

22. The integrated circuit of claim 19, wherein the first logic region and the second logic region are disposed in a row that extends in a first dimension, and wherein the first logic region and the third logic region are disposed in a column that extends in a second dimension perpendicular to the first dimension, wherein an axis extending in the second dimension intersects both the first antifuse and the third antifuse.

23. The integrated circuit of claim 19, wherein the first programming current flows through a first two programming current multiplexers of the means, the second programming current flows through a second two programming current multiplexers of the means, the third programming current flows through a third two programming current multiplexers of the means, and the fourth programming current flows through a fourth two programming current multiplexers of the means.