Complementary metal-oxide semiconductor buffer

• US 6,169,421 B1
• Filed: 05/03/1999
• Issued: 01/02/2001
• Est. Priority Date: 05/03/1999
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Applied Micro Circuits Corporation (MACOM Technology Solutions Holdings, Inc.)
• Inventors: Bryan, Thomas Clark, Dang, Harry Huy
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Le, Thong
• Application Number:
  US09/303,726
• Time in Patent Office: 610 Days
• Field of Search: 326/85, 326/87, 326/83, 326/86, 326/21, 326/62, 327/108, 365/230.08
• US Class Current: 326/83
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits

Abstract

A CMOS buffer for interfacing TTL-standard signals and capable of driving a high capacitance load such as a transmission line with low switching noise and low power consumption. The CMOS buffer includes two CMOS branch circuits that control the operation of a CMOS output device. Each branch circuit includes a first delay and a second delay greater than the first delay. The CMOS output device includes a complementary pair of MOS transistors. The first MOS transistor of the CMOS output device is operated by the first branch circuit in response to a signal that is delayed by the first or the second delay. The second MOS transistor of the CMOS output device is operated by the second branch circuit in response to delay of the signal by the second or the first delay.

Claims

1. A CMOS (complementary metal oxide semiconductor) buffer for connection to a first voltage source and a second voltage source and including an input connection and an output node, comprising:

a CMOS inverter with an input connected to the input connection and an output;

a first CMOS branch circuit connected to the output for delaying a signal by a first amount of time or a second amount of time;

a second CMOS branch circuit connected to the output for delaying the signal by the second amount of time when the first CMOS branch circuit delays the signal by the first amount of time and for delaying the signal by the first amount time when the first CMOS branch circuit delays the signal for the second amount of time; and

a CMOS output device including a first MOS transistor connected to the first CMOS branch circuit and to the output node and a second MOS transistor connected to the second CMOS branch circuit and to the output node.

2. The CMOS buffer of claim 1 further including a resistor connected to the output node.

3. The CMOS buffer of claim 2, in combination with an integrated circuit (IC) pad, the resistor connected between the output node and the IC pad.

4. The CMOS buffer of claim 1, the first CMOS branch circuit including:

a first CMOS inverter having an input connected to the output of the CMOS inverter and an output;

a second CMOS inverter having an input connected to the output of the first CMOS inverter and an output;

a first resistor with a first terminal connected to the output of the second CMOS inverter and a second terminal;

a first capacitor with a first terminal connected to the second terminal of the first resistor and a second terminal connected to the output node; and

a first MOS transistor having a gate connected to the output of the first CMOS inverter and a drain connected to the second terminal of the first resistor

wherein, the first MOS transistor of the CMOS output device has a gate connected to the second terminal of the first resistor and a drain connected to the output node.

5. The CMOS buffer of claim 4, the second CMOS branch circuit including:

a third CMOS inverter having an input connected to the output of the CMOS inverter and an output;

a fourth CMOS inverter having an input connected to the output of the third CMOS inverter and an output;

a second resistor with a first terminal connected to the output of the fourth CMOS inverter and a second terminal;

a second capacitor with a first terminal connected to the second terminal of the second resistor and a second terminal connected to the output node; and

,

a second MOS transistor having a gate connected to the output of the third CMOS inverter and a drain connected to the second terminal of the second resistor;

wherein the second MOS transistor of the CMOS output device has a gate connected to the second terminal of the second resistor and a drain connected to the output node.

6. The CMOS buffer of claim 5 further including a third resistor connected to the output node.

7. The CMOS buffer of claim 6, in combination with an integrated circuit (IC) pad, the third resistor connected between the output node and the IC pad.

8. The CMOS buffer of claim 5, wherein the first delay in the first CMOS branch circuit is through the first MOS Transistor in the first CMOS branch circuit and the first delay in the second branch circuit is through the second MOS transistor in the second branch circuit.

9. The CMOS buffer of claim 8, wherein the second delay in the first branch circuit is through the first resistor and the first capacitor and the second delay in the second CMOS branch circuit is through the second resistor and the second capacitor.

10. An integrated circuit (IC), comprising:

core circuits with a plurality of outputs; and

at least one CMOS (complementary metal oxide semiconductor) buffer that includes;

a CMOS inverter with an input connected to the input connection and an output;

a first CMOS branch circuit connected to the output for delaying a signal by a first amount of time or a second amount of time;

a second CMOS branch circuit connected to the output for delaying the signal by the second amount of time when the first CMOS branch circuit delays the signal by the first amount of time and for delaying the signal by the first amount time when the first CMOS branch circuit delays the signal for the second amount of time; and

a CMOS output device including a first MOS transistor connected to the first CMOS branch circuit and to the output node and a second MOS transistor connected to the second CMOS branch circuit and to the output node.

11. The IC of claim 10, wherein the at least one CMOS buffer includes a resistor connected to the output node.

12. The IC of claim 11, wherein the IC includes a plurality of pads, the resistor connected between one pad and the output node.

13. The IC of claim 10, wherein the first CMOS branch circuit includes:

a first CMOS inverter having an input connected to the output of the CMOS inverter and an output;

a second CMOS inverter having an input connected to the output of the first CMOS inverter and an output;

a first resistor with a first terminal connected to the output of the second CMOS inverter and a second terminal;

a first capacitor with a first terminal connected to the second terminal of the first resistor and a second terminal connected to the output node; and

a first MOS transistor having a gate connected to the output of the first CMOS inverter and a drain connected to the second terminal of the first resistor

wherein, the first MOS transistor of the CMOS output device has a gate connected to the second terminal of the first resistor and a drain connected to the output node.

14. The IC of claim 13, wherein the second CMOS branch circuit includes:

a third CMOS inverter having an input connected to the output of the CMOS inverter and an output;

a fourth CMOS inverter having an input connected to the output of the third CMOS inverter and an output;

a second resistor with a first terminal connected to the output of the fourth CMOS inverter and a second terminal;

a second capacitor with a first terminal connected to the second terminal of the second resistor and a second terminal connected to the output node; and

,

a second MOS transistor having a gate connected to the output of the third CMOS inverter and a drain connected to the second terminal of the second resistor;

wherein the second MOS transistor of the CMOS output device has a gate connected to the second terminal of the second resistor and a drain connected to the output node.

15. The IC of claim 14, wherein the IC includes a plurality of pads, the third resistor connected between one pad and the output node.

16. The IC of claim 14, wherein the first delay in the first CMOS branch circuit is through the first MOS transistor in the first CMOS branch circuit and the first delay in the second branch circuit is through the second MOS transistor in the second branch circuit.

17. The IC of claim 16 wherein the second delay in the first branch circuit is through the first resistor and the first capacitor and the second delay in the second CMOS branch circuit is through the second resistor and the second capacitor.