Receive amplifier for high speed data
First Claim
1. A receive amplifier circuit for reception of data signals on a channel, said receive amplifier having a relatively positive supply voltage and a relatively negative supply voltage, said receive amplifier comprising in combination:
- a) an input stage responsive to the data signals, said input stage comprising;
two independent complementary amplifiers, each amplifier associated with two complementary load devices, a pair of common-gate-bias nodes, said two complementary load devices having gates connected to a respective common-gate-bias node;
b) a pair of complementary output terminals for output of amplified data signals; and
c) two current-limiting devices, each current-limiting device connected to the two complementary load devices of a respective one of the amplifiers, each current-limiting device including a gate connected to a respective common-gate-bias node;
d) each of said common-gate-bias nodes being connected to a predetermined fixed voltage.
8 Assignments
0 Petitions
Accused Products
Abstract
A receive amplifier for high-speed data has a differential input stage with a very wide common-mode rejection range and low offset voltage. This input stage interfaces the differential data signals to be received. The input stage is a dual complementary differential configuration of ten MOS transistors preferably connected to provide a pair of differential inputs, a pair of differential outputs, and a single common-mode feedback input. The latter feedback input is used in the preferred embodiment to achieve balance and high common-mode rejection. Two-transistor CMOS inverters are preferably used both as amplifying stages after the input stage and as a feedback amplifier. In alternative embodiments, the nodes connected to the feedback input are instead reconnected to fixed voltages, typically one of the supply voltages or a fixed intermediate voltage, to form two independent amplifiers, one for each input node.
15 Citations
9 Claims
-
1. A receive amplifier circuit for reception of data signals on a channel, said receive amplifier having a relatively positive supply voltage and a relatively negative supply voltage, said receive amplifier comprising in combination:
-
a) an input stage responsive to the data signals, said input stage comprising;
two independent complementary amplifiers, each amplifier associated with two complementary load devices, a pair of common-gate-bias nodes, said two complementary load devices having gates connected to a respective common-gate-bias node;
b) a pair of complementary output terminals for output of amplified data signals; and
c) two current-limiting devices, each current-limiting device connected to the two complementary load devices of a respective one of the amplifiers, each current-limiting device including a gate connected to a respective common-gate-bias node;
d) each of said common-gate-bias nodes being connected to a predetermined fixed voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
Specification