Switched capacitor circuit having voltage management and method

• US 6,169,673 B1
• Filed: 01/27/1999
• Issued: 01/02/2001
• Est. Priority Date: 01/27/1999
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Kotowski, Jeffrey P., McIntyre, William James
• Primary Examiner(s): NGUYEN, MATTHEW VAN
• Application Number:
  US09/238,372
• Time in Patent Office: 706 Days
• Field of Search: 363/59, 363/60, 363/62, 307/109, 307/110, 327/325, 327/536
• US Class Current: 363/59
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

A switched capacitor circuit, for use in voltage converters and the like, which includes a switched capacitor array, a plurality of MOS transistor switches and drive circuitry for controlling the state of the switches. The drive circuitry alternates between a first phase where at least one capacitor of the array is connected by the switches between an input node and an output node and a second phase where the capacitor is connected in series between one of the output and input nodes and a third node, such as a circuit common. Boost and buck gain configurations are achieved when connected to the output and input nodes, respectively. A voltage management feature is implemented to control voltages produced in the array so that no PN junction of the transistor switches formed by a body and the drain/source regions disposed in the body becomes forward biased.

Claims

1. A switched capacitor circuit comprising:

a first capacitor having first and second terminals;

a plurality of transistor switches connected to the first and second terminals of the first capacitor; and

drive circuitry for controlling a state of the transistor switches, with the drive circuitry alternating between a first phase where the capacitor is connected by the switches in series between an input node and an output node and a second phase where the capacitor is connected in series between one of the input and output nodes and a third node, with a first current path being defined between the capacitor and the input node in the first phase having a resistance selected to be at least twice a resistance of a second current path defined between the capacitor and the output node in the first phase.

2. The switched capacitor circuit of claim 1 wherein the drive circuitry connects the capacitor to the input node and to the output node at different times when going from the second phase to the first phase, with the different time being selected so as to minimize a voltage produced on the switches.

3. The switched capacitor circuit of claim 2 wherein the drive circuitry connects the capacitor to the one of the input and output nodes and the third node at different times when going from the first phase to the second phase, with the different time being selected so as to minimize a voltage produced on the switches.

4. The switched capacitor circuit of claim 3 wherein the third node is a circuit common.

5. The switched capacitor circuit of claim 3 wherein the drive circuitry connects the capacitor in series between the output node and the third node in the second phase and wherein the drive circuitry connects the capacitor to the third node before connecting the capacitor to the output node when going to the second phase.

6. The switched capacitor circuit of claim 2 wherein the drive circuitry connects the capacitor in series between the input node and the third node in the second phase and wherein the drive circuitry in the first phase connects the capacitor to the output node before connecting the capacitor to the input node.

7. The switched capacitor circuit of claim 6 wherein the drive circuitry passes through the first phase followed by a third phase which is followed by the second phase, with the drive circuitry in the third phase connecting the capacitor in series between the input and output nodes and with a polarity opposite to that when the capacitor is connected between the input and output nodes in the first phase.

8. The switched capacitor circuit of claim 6 wherein the circuit is switchable to a low gain mode where the drive circuitry connects the capacitor in series between the output node and the third node in the second phase and to a high gain mode where the drive circuitry connects the capacitor in series between the input node and the third node in the second phase and wherein the switched capacitor circuit further includes gain limit circuitry which prevents the switched capacitor circuit from switching to the high gain mode based upon at least one of the magnitude of a voltage at the output node and the magnitude of the voltage at the input node.

9. The switched capacitor circuit of claim 8 wherein the gain limit circuitry operates based upon the magnitude of voltage at the output node relative to a magnitude of a voltage at the input node.

10. The switched capacitor circuit of claim 6 wherein the switched capacitor array is switchable to plural gain modes and wherein the switched capacitor circuit further includes gain limit circuitry which prevents the switched capacitor circuit from switching from a lower gain mode to a higher gain mode based upon at least one of a magnitude of one of a voltage at the input node and a voltage at the output node.

11. The switched capacitor circuit of claim 1 further including a second capacitor having first and second terminals and wherein the plurality of transistors switches are connected to the first and second terminals of the second capacitor and wherein the drive circuitry in the first phase connects the second capacitor in parallel with the first capacitor and in the second phase connects the second capacitor in series with the first capacitor.

12. The switched capacitor circuit of claim 11 wherein the drive circuitry connects the capacitors to the input node and to the output node at different times when going from the second phase to the first phase, with the different time being selected so as to minimize a voltage produced on the switches.

13. The switched capacitor circuit of claim 12 wherein the drive circuitry connects the capacitors to the one of the input and output nodes and the third node at different times when going from the first phase to the second phase, with the different time being selected so as to minimize a voltage produced on the switches.

14. The switched capacitor circuit of claim 13 wherein the drive circuitry connects the capacitors in series between the output node and the third node in the second phase and wherein the drive circuitry connects the capacitor to the third node before connecting the capacitor to the output node when going to the second phase.

15. The switched capacitor circuit of claim 12 wherein the drive circuitry connects the capacitors in series between the input node and the third node in the second phase and wherein the drive circuitry in the first phase connects the capacitors to the output node before connecting the capacitors to the input node.

16. The switched capacitor circuit of claim 15 wherein the drive circuitry passes through the first phase followed by a third phase which is followed by the second phase, with the drive circuitry in the third phase connecting the capacitors in series between the input and output nodes and with a polarity opposite to that when the capacitors are connected between the input and output nodes in the first phase.

17. The switched capacitor circuit of claim 16 wherein the circuit is switchable to a low gain configuration where the drive circuitry connects the capacitors in series between the output node and the third node in the second phase and to a high gain configuration where the drive circuitry connects the capacitors in series between the input node and the third node in the second phase and wherein the switched capacitor circuit further includes gain limit circuitry which prevents the switched capacitor circuit from switching to the high gain configuration based upon at least one of a magnitude of a voltage at the input and a voltage at the output node.

18. The switched capacitor circuit of claim 17 wherein the gain limit circuitry operates based upon the magnitude of voltage at the output node relative to a magnitude of a voltage at the input node.

19. The switched capacitor circuit of claim 6 wherein the circuit is switchable to a relatively low gain configuration and to a relatively high gain configuration and wherein the switched capacitor circuit further includes gain limit circuitry which prevents the switched capacitor array from switching to the high gain configuration based upon at least one of a magnitude of a voltage at the input and a voltage at the output node.

20. The switched capacitor circuit of claim 19 wherein the gain limit circuitry operates based upon the magnitude of the voltage at the output node relative to the voltage at the input node.

21. The switched capacitor circuit of claim 1 further including second and third capacitors, each having first and second terminals, and wherein the plurality of transistors switches are connected to the first and second terminals of the second and third capacitors and wherein the drive circuitry in the first phase connects the second and third capacitors in parallel with the first capacitor and in the second phase connects the second and third capacitors in series with the first capacitor.

22. The switched capacitor circuit of claim 21 wherein the drive circuitry connects the capacitors to the input node and to the output node at different times when going from the second phase to the first phase, with the different time being selected so as to minimize a voltage produced on the switches.

23. The switched capacitor circuit of claim 22 wherein the drive circuitry connects the capacitors to the one of the input and output nodes and the third node at different times when going from the first phase to the second phase, with the different time being selected so as to minimize a voltage produced on the switches.

24. The switched capacitor circuit of claim 23 wherein the drive circuitry connects the capacitors in series between the output node and the third node in the second phase and wherein the drive circuitry connects the capacitor to the third node before connecting the capacitor to the output node when going to the second phase.

25. The switched capacitor circuit of claim 22 wherein the drive circuitry connects the capacitors in series between the input node and the third node in the second phase and wherein the drive circuitry in the first phase connects the capacitors to the output node before connecting the capacitors to the input node.

26. The switched capacitor circuit of claim 25 wherein the drive circuitry passes through the first phase followed by a third phase which is followed by the second phase, with the drive circuitry in the third phase connecting the capacitors in series between the input and output nodes and with a polarity opposite to that when the capacitors are connected between the input and output nodes in the first phase.

27. The switched capacitor circuit of claim 26 wherein the circuit is switchable to a low gain configuration where the drive circuitry connects the capacitors in series between the output node and the third node in the second phase and to a high gain configuration where the drive circuitry connects the capacitors in series between the input node and the third node in the second phase and wherein the switched capacitor circuit further includes gain limit circuitry which prevents the switched capacitor circuit from switching to the high gain configuration based upon at least one of a magnitude of a voltage at the input and a voltage at the output node.

28. The switched capacitor circuit of claim 27 wherein the gain limit circuitry operates based upon the magnitude of voltage at the output node relative to a magnitude of a voltage at the input node.

29. The switched capacitor circuit of claim 26 wherein the circuit is switchable to a relatively low gain configuration and to a relatively high gain configuration and wherein the switched capacitor circuit further includes gain limit circuitry which prevents the switched capacitor array from switching to the high gain configuration based upon at least one of a magnitude of a voltage at the input node and a magnitude of a voltage at the output node.

30. The switched capacitor circuit of claim 29 wherein the gain limit circuitry operates based upon the magnitude of the voltage at the output node relative to the voltage at the input node.

31. The switched capacitor circuit of claim 1 wherein the drive circuitry in the second phase connects the capacitor in series between the output node and the third node, with a third current path being defined between the capacitor and the output node which has a resistance which is at least twice a resistance of a fourth current path defined between the capacitor and the third node.

32. The switched capacitor array of claim 1 further including a second capacitor having first and second terminals and wherein the plurality of transistor switches are connected to the first and second terminals of the second capacitor and wherein the drive circuitry in the first phase connects the second capacitor in series with the first capacitor between the input node and the first capacitor and wherein the drive circuitry in the second phase connects the first and second capacitors in parallel.

33. The switched capacitor array of claim 32 further including a third capacitor having first and second terminals and wherein the plurality of transistor switches are connected to the first and second terminals of the third capacitor and wherein the drive circuitry in the first phase connects the third capacitor in series with the first and second capacitors between the input node and the second capacitor and wherein the drive circuitry in the second phase connects the first, second and third capacitors in parallel.

34. A switched capacitor circuit comprising:

first and second capacitors, each having first and second terminals;

a plurality of transistor switches connected to the first and second terminals of the first and second capacitors; and

drive circuitry for controlling a state of the transistor switches, with the drive circuitry alternating between a first phase where the capacitors are connected by the switches in parallel between an input node and an output node and a second phase where the capacitors are connected in series between one of the input and output nodes and a third node, with first and second current paths being defined between the first and second capacitors, respectively, and the input node in the first phase and third and fourth current paths being defined between the first and second capacitors, respectively, and the output node in the first phase, with the first current path having a resistance selected to be at least twice a resistance of the third current path and the second current path having a resistance selected to be at least twice a resistance of the fourth current path.

35. A switched capacitor circuit comprising:

first and second capacitors, each having first and second terminals;

a plurality of transistor switches connected to the first and second terminals of the first and second capacitors; and

drive circuitry for controlling a state of the transistor switches, with the drive circuitry alternating between a first phase where the capacitors are connected by the switches in parallel between an input node and an output node and a second phase where the capacitors are connected in series between one of the input and output nodes and a third node and wherein the drive circuitry connects the capacitors to the input node and to the output node at different times when going from the second phase to the first phase, with the different time being selected so as to minimize a voltage produced on the switches.

36. The switched capacitor circuit of claim 35 wherein the drive circuitry connects the capacitors to the one of the input and output nodes and the third node at different times when going from the first phase to the second phase, with the different time being selected so as to minimize a voltage produced on the switches.

37. A switched capacitor circuit comprising:

a switched capacitor array connected between an input node and an output node and switchable between a relatively low and a relatively high gain configuration;

gain setting circuitry operable to select the gain configuration of the switched capacitor array;

a regulator operable to control the gain setting circuitry by changing the gain configuration in response to a change in load current demand, with the regulator limiting the gain configuration of the array to less than the high gain configuration in the presence of an increase in load current demand under predetermined operating conditions.

38. The switched capacitor circuit of claim 37 wherein the predetermined operating conditions include a magnitude of a voltage at the input node.

39. The switched capacitor circuit of claim 37 wherein the predetermined operating conditions include a magnitude of a voltage at the output node.

40. The switched capacitor circuit of claim 37 wherein the predetermined operating conditions include a magnitude of a voltage at the output node relative to a magnitude of a voltage at the input node.

41. The switched capacitor circuit of claim 37 wherein the switched capacitor array is switchable to an intermediate gain configuration intermediate the low and high gain configurations and wherein the regulator is further operable to limit the gain configuration to less than the intermediate gain configuration in the presence of an increase in load current demand under predetermined operating conditions.

42. The switched capacitor circuit of claim 37 wherein the switched capacitor array includes first and second capacitors, a plurality of transistor switches connected to the capacitors and drive circuitry for controlling a state of the switches, with the drive circuitry alternating between a first phase where the capacitors are connected by the switches in parallel between the input node and the output node and a second phase where the capacitors are connected in series between one of the input and output nodes and a third node.

43. The switched capacitor circuit of claim 42 wherein first and second current paths are defined between the capacitors and the input node in the first phase each having a resistance selected to be at least twice a resistance of third and fourth current paths defined between the capacitors and the output node in the first phase.

44. A switched capacitor circuit comprising:

a switched capacitor array connected between an input node and an output node and switchable to relatively low, intermediate and high gain configurations, with the array including a plurality of transistor switches formed in a common integrated circuit;

gain setting circuitry operable to select the gain configuration of the switched capacitor array;

a voltage regulator which controls an output voltage of the switched capacitor circuit; and

voltage management means for maintaining all voltages developed in the array within a voltage range.

45. The switched capacitor circuit of claim 44 wherein the transistor switches include N and P type MOS transistors, each having an associated body region, and wherein the voltage management means operates to prevent any PN junction associated with the body region from becoming forward biased.

46. The switched capacitor circuit of claim 45 wherein the P type transistors are formed in an N type well, with the voltage management means preventing a PN junction defined by the well and drain/source regions of the P type transistor from becoming forward biased and with the voltage management means preventing a PN junction defined by the substrate and drain/source regions of the P type transistor from becoming forward biased.

47. A method of controlling operation of a switched capacitor array, with the array including a capacitor having first and second terminals and a plurality of MOS transistor switches connected to the terminals of the capacitor, said method comprising the following:

switching the array to a first phase where a voltage across the capacitor is increased;

switching the array from the first phase to a second phase where the voltage across the capacitor is decreased; and

preventing any PN junction of the transistor switches defined by drain/source regions and a body in which the regions are formed from becoming forward biased when the array is in the first phase and in the second phase.

48. The method of claim 47 wherein the preventing includes setting a resistance of a first current path which includes the first terminal of the capacitor to be at least twice a resistance of a second current path which includes the second terminal of the capacitor when the first terminal is at a voltage more positive than a voltage at the second terminal.

49. The method of claim 47 wherein the preventing includes setting a resistance of a first current path which includes the first terminal of the capacitor to be at least twice a resistance of a second current path which includes the second terminal of the capacitor when the second terminal is at a voltage more positive than a voltage at the first terminal.

50. The method of claim 47 wherein the preventing includes controlling a relative time that the transistor switches are closed when switching to the first phase and a relative time that the transistor switches are closed when switching to the second phase.

51. The method of claim 50 wherein the controlling a relative time when switching the array to the first phase includes closing one of the transistor switches to connect the capacitor to a first node prior to closing one of the transistor switches to connect the capacitor to a second node.

52. The method of claim 51 wherein the switching the array from the first phase to a second phase connects the capacitor in series between the first node and a third node and wherein the controlling a relative time includes closing one of the transistor switches to connect the capacitor to the third node prior to closing one of the transistor switches to connect the capacitor to the first node.

53. The method of claim 47 wherein the capacitor is connected in series between a first node and a second node in the first phase and between the first node and a third node in the second phase and the preventing further includes switching the array to a third phase after switching the array to the first phase and prior to switching the array to the second phase, with the capacitor being connected in the third phase in series between the first node and second node and with a polarity opposite to that when the capacitor is connected between the first and second nodes in the first phase.

54. The method of claim 47 where the array is capable of being switched to a relatively low gain configuration and to a relatively high gain configuration and wherein the preventing further includes preventing the array from switching to the relatively high gain configuration under predetermined operating conditions.

55. The method of claim 54 wherein the predetermined operating conditions include at least one of a magnitude of a voltage at a first node and a magnitude of a voltage at a second node.

56. The method of claim 55 wherein the predetermined operating conditions include a magnitude of the voltage at the first node relative to the magnitude of the voltage at the second node.

57. A method of controlling a switched capacitor array, with the array including first, second and third capacitors, each having first and second terminals and a plurality of MOS transistor switches connected to the terminals of the capacitors, said method comprising:

switching the array to a first phase where the first, second and third capacitors are connected in parallel by the switches between an input node and an output node;

switching the array from the first phase to a second phase where at least one of the first, second and third capacitors is connected in series between one of the input and output nodes and a third node; and

preventing any PN junction of the transistor switches defined by drain/source regions and a body in which the drain/source regions are formed from becoming forward biased when the array is in the first phase and in the second phase.

58. The method of claim 57 wherein the preventing includes setting a resistance of first, second and third current paths defined between the first, second and third capacitors, respectively, to be at least twice resistances of fourth, fifth and sixth current paths defined between the first, second and third capacitors, respectively, and the output node when the array is in the first phase.

59. The method of claim 58 wherein the at least one capacitor is connected to the output node in the second phase and the preventing further includes setting a resistance of a seventh current path between the at least one capacitor and the output node to be at least twice a resistance of an eighth current path defined between the at least one capacitor and the third node.

60. The method of claim 57 where the preventing includes controlling a relative time that the transistor switches are closed when switching to the first phase and a relative time that the switches are closed when switching to the second phase.

61. The method of claim 60 wherein the controlling a relative time when switching to the first phase includes closing the switches which connect the first, second and third capacitors to the output node prior to closing the switches which connect the first, second and third capacitors to the input node.

62. The method of claim 61 wherein the switching the array from the first phase to the second phase connects the at least one capacitor to third node and wherein the controlling a relative time includes closing the switch that connects the at least one capacitor to the third node prior to closing the switch that connects the at least one capacitor to the output node.

63. The method of claim 57 wherein the at least one capacitor is connected between the input node and the third node in the second phase and the preventing further includes switching the array to a third phase after switching the array to the first phase and prior to switching the array to the second phase, with the at least one capacitor connected between the input node and the third node in the second phase being connected in the third phase in series between the input node and the output node and with a polarity opposite to that when the at least one capacitor was connected between the input node and the output node in the first phase.

64. The method of claim 57 wherein the array is capable of being switched to a relatively low gain configuration and to a relatively high gain configuration in response to an increase in load current demand and wherein the preventing includes the step of preventing the array from switching from the low gain configuration to the high gain configuration in the presence of an increase in load current demand in response to predetermined switched capacitor array conditions.

65. A switched capacitor circuit comprising:

a first capacitor having first and second terminals;

a plurality of transistor switches connected to the first and second terminals of the first capacitor; and

drive circuitry for controlling a state of the transistor switches, with the drive circuitry alternating between a first phase where the capacitor is connected by the switches in series between an input node and an output node and a second phase where the capacitor is connected in series between one of the input and output nodes and a third node, with the relative timing of the transistor switch closures for entry into the first phase and relative timing of the transistor switch closures for entry into the second phase being controlled so as to reduce a magnitude of the voltages produced at terminals of the transistor switches.

66. The switched capacitor circuit of claim 65 wherein, upon entry into the first phase from the second phase, one of the transistor switches connecting the capacitor to the output node is closed prior to closure of one of the transistor switches connecting the capacitor to the input node.

67. The switched capacitor circuit of claim 66 wherein, upon entry into the second phase, one of the transistor switches connecting the capacitor to the third node is closed prior to closure of one of the transistors connecting the capacitor to the input node.

68. The switched capacitor circuit of claim 65 wherein, upon entry into the second phase, one of the transistor switches connecting the capacitor to the third node is closed prior to closure of one of the transistors connecting the capacitor to the output node.

69. The switched capacitor circuit of claim 68 wherein, upon entry into the first phase from the second phase, one of the transistor switches connecting the capacitor to the output node is closed prior to closure of one of the transistor switches connecting the capacitor to the input node.

70. A switched capacitor circuit comprising:

at least one capacitor;

a plurality of transistor switches connected to the at least one capacitor;

a voltage regulator which limits a maximum voltage at an output node; and

drive circuitry for controlling a state of the transistor switches, with the drive circuitry alternating between a first phase where the at least one capacitor is connected by at least first and second ones of the switches in a first configuration, and a second phase where the at least one capacitor is connected in a second configuration, different than the first configuration, and wherein the drive circuitry includes timing control circuitry which causes at least the first switch to start to close after the second switch has completed closing upon entry into the first phase.

71. A switched capacitor circuit comprising:

a first capacitor having first and second terminals;

a plurality of transistor switches connected to the first and second terminals of the first capacitor;

a voltage regulator which limits a maximum voltage at an output node; and

drive circuitry for controlling a state of the transistor switches, with the drive circuitry alternating between a first phase where the capacitor is connected by the switches in series between an input node and the output node, with the first terminal of the capacitor being connected facing the input node and the second terminal of the capacitor being connected facing the output node, and a second phase where the capacitor is connected in series between the output node and a third node, with the first terminal of the capacitor facing the third node and the second terminal of the capacitor facing the output node and wherein the drive circuitry includes timing control circuitry which forces the second terminal to be connected before the first terminal upon entry into the first phase.

72. The circuit of claim 71 wherein the timing control circuitry, upon entry into the first phase, begins to turn on one of the transistor switches which connects the second terminal to the output node after one of the transistor switches that connects the first terminal to the input node has completely turned on.

73. A switched capacitor circuit comprising:

a first capacitor having first and second terminals;

a plurality of transistor switches connected to the first and second terminals of the first capacitor; and

drive circuitry for controlling a state of the transistor switches, with the drive circuitry switching from a first, to a second, and then to a third phase and then back to the first phase, with the first phase having the first capacitor connected by the switches between an input node and an output node with the first terminal facing the output node, with the second phase having the first capacitor connected between the input node and the output node with the first terminal facing the input node and with the third phase having the first capacitor connected between the input node and a third node with the first terminal facing the input node.

74. The circuit of claim 73 further including a second capacitor having first and second terminals and where, in the first phase, the drive circuitry connects the second capacitor in parallel with the first capacitor with the first terminal of the second capacitor facing the output node and where, in the third phase, connects the second capacitor in series with the first capacitor with the first terminal of the second capacitor facing the input node.

75. A switched capacitor circuit comprising:

a capacitor array having at least one capacitor;

a plurality of transistor switches connected to the at least on capacitor;

drive circuitry for controlling a state of the transistor switches so that the array will switch from a first phase to a second phase, from the second phase to a third phase and from the third phase to the first phase, with the second phase altering a voltage across the capacitor so as to reduce a magnitude of voltages produced on the transistor switches when the array is switched to the third phase.

76. The switched capacitor circuit of claim 75 where the array includes first and second capacitors each having first and second terminals and where in the first phase the first and second capacitors are connected in parallel between an input node and an output node of the array with the first terminals of the capacitors facing the output node, where in the second array phase the first and second capacitors are connected in parallel between the output node and a third node of the array with the first terminals facing the output node and where in third phase, the first and second capacitors are connected in series between the output node and the third node with the first terminals facing the output node.

77. The switched capacitor circuit of claim 75 where in the first phase the capacitor is connected in series between an input and an output node of the array with the first terminal facing the output node, where in the second phase, the capacitor is connected in series between the input and output nodes with the first terminal facing the input node and where in the third phase the capacitor is connected in series between the output node and a third array node with the first terminal facing the output node.