Invertor

• US 6,169,676 B1
• Filed: 08/21/1998
• Issued: 01/02/2001
• Est. Priority Date: 08/22/1997
• Status: Expired due to Fees

• Current Assignee: ABB Schweiz AG (ABB Limited)
• Original Assignee: Asea Brown Boveri AG (ABB Limited)
• Inventors: Ravot, Jean-François, Linhofer, Gerhard, Gaupp, Osvin, Dähler, Peter
• Primary Examiner(s): HAN, YOUNGHUIE JESSICA
• Application Number:
  US09/137,539
• Time in Patent Office: 865 Days
• Field of Search: 363/40, 363/41, 363/43, 363/39, 363/71, 363/65, 363/82, 363/83, 361/42
• US Class Current: 363/71
• CPC Class Codes: H02M 7/49 Combination of the output voltage waveforms of a plurality of converters

Abstract

An invertor having a plurality of invertor bridges which operate in parallel and whose output voltages are summed. The invertor bridges are driven with pulse duration modulation according to an auxiliary control voltage. The auxiliary control voltages of the individual invertor bridges have a constant phase difference between one another. The output voltages of the bridges are summed by a center tap which is grounded by a ground connection. Effective suppression of the common-mode current distortion is achieved by having the switch arranged in the ground connection.

Claims

1. An inverter comprising:

a plurality of invertor bridges, which operate in parallel on a same DC voltage intermediate circuit;

summer means for summing output voltages of the invertor bridges, and having a center tap, which can be grounded via a ground connection;

the invertor bridges each being driven with pulse duration modulation according to an auxiliary control voltage, and auxiliary control voltages of the individual invertor bridges having a constant phase difference between one another; and

switching means arranged in the ground connection in order to attenuate or suppress in-phase interference currents flowing via the ground connection and interference voltages associated with said interference currents.

2. The invertor as claimed in claim 1, wherein the switching means comprises an inductor designed as a saturable reactor.

3. The invertor as claimed in claim 2, wherein the voltage-time integral of the inductor is matched to the expected voltage-time integral of the interference voltages and interference currents during normal operation.

4. The inventor as claimed in claim 3, wherein a resistor is arranged in the ground connection, and wherein the switching means in the ground connection are connected in series with the resistor.

5. The invertor as claimed in claim 3, wherein the summation means comprises a transformer, which has a number of primary windings and associated secondary windings which corresponds to the number of invertor bridges, wherein each invertor bridge is respectively connected on the output side to a primary winding, and wherein the secondary windings are connected in series for the purpose of summing the output voltages.

6. The use of an invertor as claimed in claim 3 in a converter having a DC voltage intermediate circuit.

7. The inventor as claimed in claim 2, wherein a resistor is arranged in the ground connection, and wherein the switching means in the ground connection are connected in series with the resistor.

8. The invertor as claimed in claim 2, wherein the summation means comprises a transformer, which has a number of primary windings and associated secondary windings which corresponds to the number of invertor bridges, wherein each invertor bridge is respectively connected on the output side to a primary winding, and wherein the secondary windings are connected in series for the purpose of summing the output voltages.

9. The use of an invertor as claimed in claim 2 in a converter having a DC voltage intermediate circuit.

10. The invertor as claimed in claim 1, wherein the switching means comprises a thyristor switch.

11. The inventor as claimed in claim 10, wherein a resistor is arranged in the ground connection, and wherein the switching means in the ground connection are connected in series with the resistor.

12. The invertor as claimed in claim 10, wherein the summation means comprises a transformer, which has a number of primary windings and associated secondary windings which corresponds to the number of invertor bridges, wherein each invertor bridge is respectively connected on the output side to a primary winding, and wherein the secondary windings are connected in series for the purpose of summing the output voltages.

13. The use of an invertor as claimed in claim 10 in a converter having a DC voltage intermediate circuit.

14. The invertor as claimed in claim 1, wherein a resistor is arranged in the ground connection, and wherein the switching means in the ground connection is connected in series with the resistor.

15. The invertor as claimed in claim 14, wherein the summation means comprises a transformer, which has a number of primary windings and associated secondary windings which corresponds to the number of invertor bridges, wherein each invertor bridge is respectively connected on the output side to a primary winding, and wherein the secondary windings are connected in series for the purpose of summing the output voltages.

16. The use of an invertor as claimed in claim 14 in a converter having a DC voltage intermediate circuit.

17. The invertor as claimed in claim 1, wherein the summation means comprises a transformer, which has a number of primary windings and associated secondary windings which corresponds to the number of invertor bridges, wherein each invertor bridge is respectively connected on the output side to a primary winding, and wherein the secondary windings are connected in series for the purpose of summing the output voltages.

18. The invertor as claimed in claim 17, wherein 2n (n=1,2,3, . . . ) invertor bridges and primary windings and secondary windings are provided, and wherein the center tap is arranged between the n-th and the (n+1)-th secondary winding.

19. The use of an invertor as claimed in claim 17 in a converter having a DC voltage intermediate circuit.

20. The use of an invertor as claimed in claim 1 in a converter having a DC voltage intermediate circuit.

21. An inverter comprising:

a plurality of invertor bridges operating in parallel on a same DC voltage intermediate circuit;

a summer configured to sum output voltages of the plurality of invertor bridges, and having a center tap which can be grounded via a ground connection;

said invertor bridges each being driven with pulse duration modulation according to an auxiliary control voltage, and auxiliary control voltages of the individual invertor bridges having a constant phase difference between one another; and

a switching mechanism configured to attenuate or suppress in-phase interference currents flowing via the ground connection and interference voltages associated with said interference currents.

22. The inverter as claimed in claim 21, wherein the switching mechanism comprises an inductor designed as a saturable reactor.

23. The inverter as claimed in claim 22, wherein a voltage-time integral of the inductor is matched to an expected voltage-time integral of the interference voltages and interference currents during normal operation.

24. The invertor as claimed in claim 21, wherein the switching mechanism comprises a thyristor switch.

25. The inverter as claimed in claim 21, wherein a resistor is arranged in the ground connection, and is connected in series with the switching mechanism.

26. The invertor as claimed in claim 21, wherein the summer comprises a transformer, which has a number of primary windings and associated secondary windings corresponding to the number of inverter bridges,

wherein each inverter bridge is respectively connected on an output side to a primary winding, and

wherein the secondary windings are connected in series so as to sum the output voltages.

27. The invertor as claimed in claim 26, further comprising:

2n (n=1, 2, 3, . . . ) inverter bridges and primary windings and secondary windings,

wherein the center tap is arranged between the n-th and the (n+1)-th secondary winding.

28. The use of an invertor as claimed in claim 21 in a converter having a DC voltage intermediate circuit.