Solid-state memory with magnetic storage cells

• US 6,169,686 B1
• Filed: 11/20/1997
• Issued: 01/02/2001
• Est. Priority Date: 11/20/1997
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Bhattacharyya, Manoj K., Anthony, Thomas C., Nickel, Janice, Tran, Lung T., Brug, James A.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US08/974,925
• Time in Patent Office: 1,139 Days
• Field of Search: 365/157, 365/158, 365/171, 365/173, 365/170
• US Class Current: 365/171
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10N 50/01 Manufacture or treatment

Abstract

A solid-state memory including an array of magnetic storage cells and a set of conductors. The process steps that pattern the conductors also patterns the magnetic layers in the magnetic storage cells thereby avoiding the need to employ precise alignment between pattern masks.

Claims

1. A memory, comprising:

array of magnetic storage cells each for storing a bit of information, each magnetic storage cell having an active layer for storing a rotatable magnetization and a reference layer having a fixed magnetization wherein the reference layers are provided by a set of magnetic films in the array arranged as continuous strips to prevent magnetic fields from emanating from the reference layers and affecting magnetic fields in the active layers;

a set of top conductors coupled to the magnetic storage cells wherein a patterning step that formed the top conductors also patterned the magnetic storage cells.

2. The memory of claim 1, wherein the patterning step patterned the active layer in each of the magnetic storage cells.

3. The memory of claim 1, wherein the patterning step patterned the active layer and a dielectric region in each of the magnetic storage cells.

4. The memory of claim 1, wherein the patterning step patterned the active layer and a dielectric region and the magnetic film in each of the magnetic storage cells.

5. The memory of claim 1, further comprising a set of bottom conductors that are substantially orthogonal to the top conductors and that are coupled to the magnetic storage cells wherein a patterning step that formed the bottom conductors also patterned the active layer and a dielectric region and the magnetic film in each of the magnetic storage cells.

6. The memory of claim 1, further comprising a dielectric layer that prevents the top conductors from causing short circuits among layers of the magnetic storage cells.

7. The memory of claim 5, further comprising:

current sensing amplifier having an input coupled to one of the bottom conductors to sense an electrical current from one of the magnetic storage cells being read;

circuitry for applying a potential to each of the bottom conductors not coupled to the magnetic storage cell being read such that the potentials of the bottom conductors not coupled to the magnetic storage cell being read are substantially equal to the potential of the input to the current sense amplifier to reduce an amount of leakage electrical current among the bottom conductors.

8. The memory of claim 7, wherein the circuitry for applying a potential to each of the bottom conductors not coupled to the magnetic storage cell being read includes at least one transistor.

9. The memory of claim 7, wherein the circuitry for applying a potential to each of the bottom conductors not coupled to the magnetic storage cell being read includes at least one other current sense amplifier having an input with the potential.

10. The memory of claim 1, wherein each magnetic storage cell includes a diode structure that reduces an amount of leakage electrical current during read operations in the memory.