Method and system for modeling, predicting and optimizing chemical mechanical polishing pad wear and extending pad life

• US 6,169,931 B1
• Filed: 07/29/1998
• Issued: 01/02/2001
• Est. Priority Date: 07/29/1998
• Status: Expired due to Fees

• Current Assignee: Southwest Research Institute
• Original Assignee: Southwest Research Institute
• Inventors: Runnels, Scott R.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Patel, Nitin
• Application Number:
  US09/124,339
• Time in Patent Office: 888 Days
• Field of Search: 700/97, 700/121, 700/164
• US Class Current: 700/97
• CPC Class Codes: B24B 37/24 characterised by the composition or properties of the pad materials
• CPC Class Codes: B24B 37/26 characterised by the shape of the lapping pad surface, e.g. grooved

Abstract

A computer implemented system and method for modeling, predicting and optimizing a Chemical Mechanical Polishing (CMP) system for polishing semiconductor wafers and other types of substrates used in the manufacture of integrated circuits. The method and system comprises a pad wear and conditioning model that predicts the polishing effectiveness of each sampling point on the polish pad based upon the polishing pad and substrate parameters, the pressure and speed between the wafer and the polish pad, and on the amount of polishing the point has performed in a simulated CMP hardware configuration using the CMP system recipe settings. The model determines the change in pad roughness and thickness for each sampling point on the pad. The model results are used along with wafer scale uniformity and feature scale planarity model results to optimize pad life and determining optimal recipe settings for the CMP process.

Claims

1. A method for modeling, predicting and optimizing a Chemical Mechanical Polishing (CMP) system for polishing semiconductor wafers and other types of substrates used in the manufacture of integrated circuits, in a computer program running on a computer processor, the method comprising the steps of:

a. inputting polishing pad and semiconductor wafer and substrate parameters;

b. defining a set of pad sampling points on a CMP polish pad;

c. simulating the CMP hardware configuration and inputting CMP system recipe settings;

d. using pressure and speed between the wafer and the polish pad; and

e. defining a pad wear and conditioning model that predicts the polishing effectiveness of each sampling point on the polish pad based upon the polishing pad and substrate parameters, the pressure and speed between the wafer and the polish pad, and on the amount of polishing the point has performed in the simulated CMP hardware configuration using the CMP system recipe settings, the model comprising

i. determining the change in pad roughness for each sampling point on the pad using a pad wear model;

ii. determining the change in pad thickness for each sampling point on the pad using a pad conditioning model.

2. The method of claim 1 wherein pad roughness for each sampling point is

represented as a pad roughness variable.

3. The method of claim 2, further comprising:

a. defining a set of wafer sampling points on a semiconductor wafer that correspond to the set of pad sampling points; and

b. predicting the rate of material removed from the wafer at each wafer sampling point as a function of the pressure and relative speed between the wafer and the pad at that sampling point, and as a function of the pad roughness variable at that sampling point.

4. The method of claim 2, further comprising:

a. defining a set of wafer sampling points on a semiconductor wafer that correspond to the set of pad sampling points; and

b. using the pad roughness variable for each pad sampling point as computed in the pad wear model as an input to a uniformity model, that predicts the material removal rate of the material removed from the surface of a semiconductor wafer at each wafer sampling point.

5. The method of claim 1, the pad conditioning model further comprising:

a. representing the polish pad as having a relatively stiff top pad planar surface connected to and located just above a relatively soft base pad planar surface having a thickness greater than the top pad planar surface;

b. predicting the change in the thickness of the top pad planar surface for each pad sampling point as a function of the polishing pad and substrate parameters, the pressure and speed between the wafer and the polish pad, the amount of conditioning performed on the top pad, and on the amount of polishing the pad sampling point has performed in the simulated CMP hardware configuration using the CMP system recipe settings, and determining the resulting thickness of the top pad planar surface for each sampling point;

c. predicting the change in thickness of the base pad planar surface as a function of the polishing pad and substrate parameters, the pressure and speed between the wafer and the polish pad, and the amount of polishing the pad sampling point has performed in the simulated CMP hardware configuration using the CMP system recipe settings, and determining the resulting thickness of the base pad planar surface for each sampling point; and

d. using the resulting thickness of the top pad planar surface and the base pad planar surface to compute a pad thickness variable for each sampling point.

6. The method of claim 5, further comprising:

a. inputting pre-polish wafer topography data;

b. defining a set of wafer sampling points on a semiconductor wafer that correspond to the set of pad sampling points; and

c. using the pad thickness variable for each pad sampling point as computed in the pad conditioning model and the material removal rate computed in the uniformity model as an input to a planarity model for predicting the erosion of features on a semiconductor wafer at each wafer sampling point.

7. The method according to claim 6, wherein the planarity model is a two-dimensional planarity model.

8. The method according to claim 6, wherein the planarity model is a three-dimensional model.

9. The method of claim 1, the pad wear model further comprising:

a. representing the polish pad as having a relatively stiff top pad planar surface connected to and located just above a relatively soft base pad planar surface with a thickness greater than the top pad planar surface;

b. predicting the change in the thickness of the top pad planar surface for each pad sampling point as a function of the polishing pad and substrate parameters, the pressure and speed between the wafer and the polish pad, the amount of conditioning performed on the top pad, and the amount of polishing the pad sampling point has performed in the simulated CMP hardware configuration using the CMP system recipe settings; and

c. using the predicted change in thickness to compute a pad roughness variable, which represents the roughness of each pad sampling point as a function of the polishing pad and substrate parameters, the pressure and speed between the wafer and the polish pad, the amount of conditioning performed on the top pad planar surface, and on the amount of polishing the pad sampling point has performed in the simulated CMP hardware configuration using the CMP system recipe settings.

10. The method according to claim 9, further comprising predicting the throughput for the CMP process in the uniformity model.

11. The method according to claim 1, the pad wear model further comprising:

a. representing the polish pad as having a relatively stiff top pad planar surface connected to and located just above a relatively soft base pad planar surface with a thickness greater than the top pad planar surface;

b. determining a minimum roughness value for the top pad planar surface of the polish pad, which represents the top pad'"'"'s minimum effectiveness in removing material from a semiconductor wafer during the CMP process;

c. determining a maximum roughness value for the top pad planar surface of the polish pad, which represents the top pad'"'"'s maximum effectiveness in removing material from a semiconductor wafer during the CMP polishing process;

d. setting an effective roughness value for each sampling point to the maximum roughness value upon polish process initiation;

e. simulating the conditioning process performed on the top pad planar surface to increase the effective roughness value when the roughness value is less than the maximum roughness value and greater than or equal to the minimum value; and

f. predicting and updating the effective roughness value for each pad sampling point as it changes during the CMP process and conditioning process.

12. The method according to claim 11, the simulating the conditioning process further comprising:

a. computing a polish wear model for each sampling point as a function of a pad degradation rate multiplied by the effective roughness value for each pad sampling point times the rate the at work is done on the top pad planar surface by the wafer; and

b. the rate at which work is done is a function of the pressure and speed between the wafer and the polish pad for each sampling point during the polishing process.

13. The method according to claim 12, further comprising:

a. computing the pressure distribution between the pad and the wafer; and

b. setting the pressure between the wafer and the polish pad for each sampling point to the pressure distribution when the pad is contact with the wafer.

14. The method according to claim 12 using the polish wear model to calculate the effective roughness value for each sampling point by computing the difference between the maximum roughness value and the minimum value as a function of the rate at which work is done, and the pad degradation rate over time summed with the minimum effective roughness value.

15. The method according to claim 14, further comprising setting the pad degradation rate to zero when the pad sampling point is not under the wafer.

16. The method according to claim 15, further comprising setting the pad restoration rate to zero when the pad sampling point is not under the conditioning device.

17. The method according to claim 11, further comprising:

a. modeling the pad conditioning process by using a pad restoration rate times the effective roughness value for each sampling point minus the maximum roughness value, times the rate that work is done on the top pad surface by the wafer; and

b. the rate at which work is done is a function of the pressure and speed between the wafer and the polish pad for each sampling point during the polishing process.

18. A method for modeling, predicting and optimizing a Chemical Mechanical Polishing (CMP) system for polishing semiconductor wafers and other types of substrates used in the manufacture of integrated circuits, in a computer program running on a computer processor, the method comprising the steps of:

a. inputting polishing pad and semiconductor wafer and substrate parameters;

b. defining a set of pad sampling points on a CMP polish pad;

c. simulating the CMP hardware configuration and inputting CMP system recipe settings;

d. using pressure and speed between the wafer and the polish pad;

e. defining a pad wear and conditioning model that predicts the polishing effectiveness of each sampling point on the polish pad based upon the polishing pad and substrate parameters, the pressure and speed between the wafer and the polish pad, and on the amount of polishing the point has performed in the simulated CMP hardware configuration using the CMP system recipe settings, the model comprising

i. determining the change in pad roughness for each sampling point on the pad using a pad wear model;

ii. determining the change in pad thickness for each sampling point on the pad using a pad conditioning model.

f. inputting pre-polish wafer topography data;

g. defining a set of wafer sampling points on a semiconductor wafer that correspond to the set of pad sampling points;

h. using the pad roughness for each pad sampling point as computed in the pad wear model as an input to a uniformity model for predicting the material removal rate for the material removed from the surface of a semiconductor wafer at each wafer sampling point; and

i. using the pad thickness variable for each pad sampling point as computed in the pad conditioning model and the material removal rate computed in the uniformity model as an input to a planarity model for predicting the erosion of features on a semiconductor wafer at each wafer sampling point.

19. The method according to claim 18, further comprising optimizing pad life and determining an optimal CMP recipe setting.

20. The method according to claim 19, the steps of optimizing pad life and determining the optimal recipe setting further comprising:

a. entering performance requirements for uniformity, planarity and throughput;

b. forming an optimal recipe solution;

c. modeling the polishing of a set of wafers predicting uniformity, planarity, pad wear, pad conditioning and pad thinning;

d. performing steps b and c until the model is not within the performance requirements entered;

e. determining the number of wafers polished;

f. forming a new optimal recipe solution;

g. performing steps c through f until the optimal recipe solution converges; and

h. saving the optimal recipe.

21. The method according to claim 20, wherein the entering of performance requirements for uniformity, planarity and throughput is by a user through a graphical user interface.

22. The method according to claim 20, wherein the entering of performance requirements for uniformity, planarity and throughput is from a previous pad conditioning and wear model system result.

23. The method according to claim 20, further comprising optimizing pad life by determining an optimal roughness of the polish pad to both extend pad life and achieve a predetermined uniformity of the wafer after the CMP process.

24. The method according to claim 20, further comprising optimizing pad life by determining an optimal top pad stiffness and base pad compressibility to both extend pad life and achieve a predetermined planarity of the wafer after the CMP process.

25. The method according to claim 19, further comprising using the predicted erosion of features and predicted material removed from a semiconductor wafer at each sampling point to predict polish pad wear and determine optimal CMP system parameters including the optimal pad parameters, optimal frequency of pad conditioning, geometry of the CMP hardware configuration and CMP recipe settings to optimize polish pad life.

26. The method according to claim 25, using the predicted polish pad wear to optimize pad life further comprising determining optimal settings to enhance polish pad life:

a. changing polish pad material properties;

b. changing the polish pad parameters;

c. determining an optimal frequency of conditioning the top pad to maintain constant uniformity;

d. changing the CMP process recipe settings; and

e. varying the simulation of the CMP hardware configuration.

27. The method according to claim 26, the changing the CMP process setting step further comprises:

a. varying the pressure between the pad and the wafer during polishing; and

b. varying the speed between the pad and the wafer during polishing.

28. The method according to claim 25 wherein the optimal settings to enhance polish pad life are input into the pad conditioning and wear model, uniformity model and planarity model to predict the uniformity and planarity of the wafer after the CMP process.

29. The method according to claim 25, further comprising:

a. predicting the decay in material removal rate during the CMP polish process;

b. determining the optimal conditioning frequency of the pad to roughen its surface and restore the pad'"'"'s original material removal rate; and

c. determining the optimal time of pad replacement.