Method of manufacture of CMOS device using additional implant regions to enhance ESD performance

• US 6,171,891 B1
• Filed: 02/27/1998
• Issued: 01/09/2001
• Est. Priority Date: 02/27/1998
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Shih, Tiaw-Ren, Lee, Jian-Hsing, Wu, Yi-Hsun
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): GUERRERO, MARIA F
• Application Number:
  US09/031,653
• Time in Patent Office: 1,047 Days
• Field of Search: 438/223, 438/224, 438/227, 438/230, 438/232, 438/233, 438/309, 438/357, 438/358, 438/369, 438/371, 438/523, 438/542, 438/621, 438/197
• US Class Current: 438/197
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method of forming a semiconductor memory device formed on a semiconductor substrate with an N-well and a P-well comprises the following steps. Form over a substrate the combination of a gate oxide layer and a gate layer patterned into gate stacks with sidewalls for an NMOS FET device over a P-well in the substrate and a PMOS FET device over an N-well. Form P− lightly doped S/D regions in the N-well and N− lightly doped S/D regions in the P-well. Form spacers on the sidewalls of the gate stacks. Thereafter form deep N− lightly doped S/D regions in the P-well, and form deep P− lightly doped S/D regions in the N-well. Form heavily doped P++ regions self-aligned with the gate below future P+ S/D sites to be formed self-aligned with the spacers in the N-well, and form heavily doped N++ regions self-aligned with the gate below future N+ S/D sites to be formed self-aligned with the spacers in the P-well.

Claims

1. A method of forming a semiconductor memory device on a semiconductor substrate within which are formed an N-well and a P-well within which source/drain sites are formed comprising the steps as follows:

forming a gate oxide layer and a gate electrode layer patterned into a gate electrode stack with sidewalls over the semiconductor substrate with an N-well and a P-well,

forming P−

lightly doped source/drain regions in the N-well,

forming N−

lightly doped source/drain regions in the P-well,

forming spacers on the gate electrode sidewalls,

forming N++ type regions below respective source/drain sites and forming P++ type regions below respective source/drain sites,

forming the N+ type source/drain regions in the P-well in the source/drain sites above the N++ type regions,

forming the P+ type source/drain regions in the N-well in the source/drain sites above the P++ type regions, and

forming additional, deep, lightly doped N−

regions in the N-well self-aligned with the spacers below the P++ type regions, and

forming additional, deep, lightly doped P−

regions in the N-well self-aligned with the spacers below the N++ type regions.

2. The method of claim 1 including forming P−

/N++ junctions below the N+ source/drain regions in the P-well and forming N−

/P++ junctions below the P+ source/drain regions in the N-well from the heavily doped N++/P++ regions and the additional, deep, lightly doped N− and

P-regions.

3. A method of forming a semiconductor memory device formed on a semiconductor substrate covered with a gate oxide layer upon which are formed gate electrode stacks, with an N-well formed in the semiconductor substrate with P−

lightly doped source/drain regions formed self-aligned with gate electrode stacks, with P+ source/drain sites, with heavily doped P++ regions below the P+ source/drain sites, and additional, deep, lightly doped N−

regions located deep below the heavily doped P++ regions and a P-well formed in the semiconductor substrate with N−

lightly doped source/drain regions formed self-aligned with gate electrode stacks, with N+ source/drain sites, with heavily doped N++ regions below the N+ source/drain sites, and additional, deep, lightly doped P−

regions located deep below the heavily doped N++ regions comprising the steps as follows;

forming over the semiconductor substrate a combination of a gate oxide layer and a gate electrode layer patterned into gate electrode stacks with sidewalls for an NMOS FET device over a P-well in the semiconductor substrate and a PMOS FET device over an N-well,

forming P−

lightly doped source/drain regions in the N-well self-aligned with the gate electrode stacks therein, and forming N−

lightly doped source/drain regions in the P-well self-aligned with the gate electrode stacks therein,

forming spacers on the sidewalls of the gate electrode stacks,

thereafter forming the additional, deep, lightly doped N-regions in the P-well, and forming the additional, deep, lightly doped P−

regions in the N-well,

forming heavily doped P++ regions self-aligned with the gate electrode below P+ source/drain sites self-aligned with the spacers in the N-well, and forming heavily doped N++ regions self-aligned with the gate electrode below future N+ source/drain sites to be formed self-aligned with the spacers in the P-well,

forming the N+ type source/drain regions in the P-well in the source/ drain sites,

forming the P+ type source/drain regions in the N-well in the source/drain sites, and

forming P−

/N++ junctions below the N+ source/drain regions in the P-well and forming N−

/P++ junctions below the P+ source/drain regions in the N-well from the heavily doped N++/P++ regions and the additional, deep, lightly doped N−

regions and the additional, deep, lightly doped P-regions.

4. A method of forming a semiconductor memory device formed on a semiconductor substrate with a gate oxide layer upon which are formed gate electrode stacks, an N-well formed in the semiconductor substrate with P−

lightly doped source/drain regions formed self-aligned with gate electrode stacks, with P+ source/drain sites, with heavily doped P++ regions below the P+ source/drain sites, and additional, deep, lightly doped N−

doped regions located deep below the heavily doped P++ regions and a P-well formed in the semiconductor substrate with N−

lightly doped source/drain regions formed self-aligned with gate electrode stacks, with N+ source/drain sites, with heavily doped N++ regions below the N+ source/drain sites, and additional deep, lightly doped P−

regions located deep below the heavily doped N++ regions, comprising the steps as follows;

forming over the semiconductor substrate a combination of the gate oxide layer and a gate electrode layer patterned into the gate electrode stacks with sidewalls for an NMOS FET device over a P-well in the semiconductor substrate and a PMOS FET device over an N-well,

forming P−

lightly doped source/drain regions self-aligned with the gate electrode stacks in the N-well,

forming N−

lightly doped source/drain regions self-aligned with the gate electrode stacks in the P-well,

forming spacers on the sidewalls of the gate electrode stacks,

thereafter forming the additional, deep, lightly doped N−

regions in the P-well, and forming the additional, deep, lightly doped P−

regions in the N-well,

forming heavily doped P++ regions below the P+ source/drain sites self-aligned with the spacers in the N-well, and forming heavily doped N++ regions below the N+ source/drain sites self-aligned with the spacers in the P-well,

forming the N+ type source/drain regions in the P-well in the source/drain sites,

forming the P+ type source/drain regions in the N-well in the source/drain sites,

forming refractory metal silicide layers over the gate electrode layers, and

forming P−

/N++ junctions below the N+ source/drain regions in the P-well and forming N−

/P++ junctions below the P+ source/drain regions in the N-well from the heavily doped N++/P++ regions and the additional, deep, lightly doped N−

regions and the additional, deep, lightly doped P−

regions.

5. The method of claim 4 including forming refractory metal silicide layers over the source/drain regions.

6. A method of forming a semiconductor memory device formed on a semiconductor substrate with a sate oxide layer upon which are formed gate electrode stacks, an N-well formed in the semiconductor substrate with P−

lightly doped source/drain regions formed self-aligned with gate electrode stacks, with P+ source/drain sites, with heavily doped P++ regions below the P+ source/drain sites, and additional, deep, lightly doped N−

regions located deep below the heavily doped P++ regions and a P-well formed in the semiconductor substrate with N−

lightly doped source/drain regions formed self-aligned with gate electrode stacks, with N+source/drain sites, with heavily doped N++ regions below the N+source/drain sites, and additional, deep, lightly doped P−

regions located deep below the heavily doped N++ regions, comprising the steps as follows;

forming over the semiconductor substrate a combination of the gate oxide layer and a gate electrode layer patterned into the gate electrode stacks with sidewalls for an NMOS FET device over a P-well in the semiconductor substrate and a PMOS FET device over an N-well,

forming P−

lightly doped source/drain regions self-aligned with the gate electrode stacks in the N-well,

forming N−

lightly doped source/drain regions self-aligned with the gate electrode stacks in the P-well,

forming spacers on the sidewalls of the gate electrode stacks,

thereafter forming the additional, deep, lightly doped N−

regions in the P-well, and forming the additional, deep, lightly doped P−

regions in the N-well,

forming heavily doped P++ regions below the P+ source/drain sites self-aligned with the spacers in the N-well, and forming heavily doped N++ regions below the N+ source/drain sites self-aligned with the spacers in the P-well,

forming the N+ type source/drain regions in the P-well in the source/drain sites,

forming the P+ type source/drain regions in the N-well in the source/drain sites,

forming refractory metal silicide layers over the gate electrode layers,

with the additional, deep, lightly doped N− and

P−

regions being formed to a depth from about 2000 Å

to about 3,000 Å

below the surface of the semiconductor substrate, and

with the N++ and P++ regions being formed to a depth from about 1,000 Å

to about 2000 Å

below the surface of the semiconductor substrate.

7. A method of forming a semiconductor memory device formed on a semiconductor substrate with a gate oxide layer upon which are formed gate electrode stacks, an N-well formed in the semiconductor substrate with P−

lightly doped source/drain regions formed self-aligned with gate electrode stacks, with P+ source/drain sites, with heavily doped P++ regions below the P+ source/drain sites, and additional, deep, lightly doped N−

regions located deep below the heavily doped P++ regions and a P-well formed in the semiconductor substrate with N−

lightly doped regions formed self-aligned with gate electrode stacks, with N+ source/drain sites, with heavily doped N++ regions below the N+ source/drain sites, and additional, deep, lightly doped P−

regions located deep below the heavily doped N++ regions, comprising the steps as follows;

forming over the semiconductor substrate a combination of the gate oxide layer and a gate electrode layer patterned into the gate electrode stacks with sidewalls for an NMOS FET device over a P-well in the semiconductor substrate and a PMOS FET device over an N-well,

forming P−

lightly doped source/drain regions self-aligned with the gate electrode stacks in the N-well,

forming N−

lightly doped source/drain regions self-aligned with the gate electrode stacks in the P-well,

forming spacers on the sidewalls of the gate electrode stacks,

thereafter forming the additional, deep, lightly doped N−

regions in the P-well and forming the additional, deep, lightly doped P-regions in the N-well,

forming heavily doped P++ regions below the P+ source/drain sites self-aligned with the spacers in the N-well, and forming heavily doped N++ regions below the N+ source /drain sites self-aligned with the spacers in the P-well,

forming the N+ type source/drain regions in the P-well in the source/drain sites,

forming the P+ type source/drain regions in the N-well in the source /drain sites,

forming refractory metal silicide layers over the gate electrode layers, as follows;

forming refractory metal silicide layers over the source/drain regions,

forming P−

/N++ junctions below the N+ source/drain regions in the P-well and forming N−

/P++ junctions below the P+ source/drain regions in the N-well from the heavily doped N++/P++ regions and the additional, deep, lightly doped N−

regions and the additional deep, lightly doped P-regions,

with the deep lightly doped N− and

P−

regions formed to a depth from about 2000 Å

to about 3,000 Å

below the surface of the semiconductor substrate, and

with the N++ and P++ regions formed to a depth from about 1,000 Å

to about 2,000 Å

below the surface of the semiconductor substrate.