Method for forming a semiconductor device

• US 6,171,910 B1
• Filed: 07/21/1999
• Issued: 01/09/2001
• Est. Priority Date: 07/21/1999
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Wu, Wei, Maiti, Bikas, Hobbs, Christopher C.
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): García, Joannie Adelle
• Application Number:
  US09/358,213
• Time in Patent Office: 538 Days
• Field of Search: 438/197, 438/198, 438/275, 438/926, 438/195, 438/585, 438/FOR.193
• US Class Current: 438/275
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

Abstract

First and second dummy structures (201 and 202) are formed over a semiconductor device substrate (10). In one embodiment, portions of the first dummy structure (201) are removed and replaced with a first conductive material (64) to form a first gate electrode (71) and portions of second dummy structure (202) are removed and replaced with a second conductive material (84) to form a second gate electrode (91). In an alternate embodiment, the dummy structures (201 and 202) are formed using a first conductive material (164) that is used to form the first electrode (71). The second electrode is then formed by removing the first conductive material (164) from dummy structures (202) and replacing it with a second conductive material (84). In accordance with embodiments of the present invention, the first conductive material and the second conductive material are different conductive materials.

Claims

1. A method for forming a semiconductor device comprising:

forming first and second dummy structures over a semiconductor device substrate,

forming source and drain regions, wherein alignment of source and drain regions is obtained using the first and second dummy structures;

removing portions of the first dummy structure to form a first opening;

filling the first opening with a first conductive material, wherein portions of the first conductive material form a first gate electrode;

removing portions of the second dummy structure to form a second opening; and

filling the second opening with a second conductive material, wherein portions of the second conductive material forms a second gate electrode, and wherein the first conductive material and the second conductive material are different conductive materials.

2. The method of claim 1, wherein the source and drain regions include elevated source and drain regions.

3. The method of claim 2, wherein the source and drain regions include silicided source and drain regions.

4. The method of claim 1 further comprising:

forming a first gate dielectric between the first gate electrode and the semiconductor device substrate; and

forming a second gate dielectric between the second gate electrode and the semiconductor device substrate, wherein a thickness of the first gate dielectric and a thickness of the second gate dielectric are different.

5. The method of claim 1, wherein at least one of the first dummy structure and the second dummy structure includes a material selected from a group consisting of amorphous silicon, polysilicon, germanium, and silicon germanium.

6. The method of claim 1, wherein at least one of the first conductive material and the second conductive material includes a metal selected from a group consisting of aluminum, copper, titanium, tantalum, tungsten, molybdenum, platinum, palladium, osmium, iridium, and ruthenium.

7. The method of claim 1, further comprising forming an interconnect layer and a passivation layer over the semiconductor device substrate.

8. The method of claim 1, further comprising:

forming a dielectric layer overlying the first and second dummy structures;

polishing the dielectric layer to expose portions of the first and second dummy structures;

forming a first capping layer over the second dummy structure prior to removing portions of the first dummy structure; and

forming a second capping layer over the first gate electrode prior to removing portions of the second dummy structure.

9. A method for forming a semiconductor device comprising:

forming first and second dummy structures over a semiconductor device substrate;

forming a dielectric layer overlying the first and second dummy structures;

polishing the dielectric layer to expose a first portion of a stop material underlying a portion of the dielectric layer;

removing portions of the first dummy structure to define a first opening;

filling the first opening with a first conductive material;

removing portions of the first conductive material to at least partially form a first gate electrode;

removing surface portions of the semiconductor device substrate to expose a second portion of the stop material;

removing portions of the second dummy structure to define a second opening;

filling the second opening with a second conductive material, wherein the second conductive material is different from the first conductive material; and

polishing the second conductive material to form a second gate electrode.

10. The method of claim 9, wherein the stop material includes portions of at least one of the first and second dummy structures.

11. The method of claim 9, wherein the stop material includes portions of a capping layer formed overlying the first and second dummy structures.

12. The method of claim 11, wherein the capping layer includes a material selected from a group consisting of silicon nitride, titanium oxide, tantalum oxide, aluminum oxide, zirconium oxide, germanium nitride, and aluminum nitride.

13. The method of claim 11, wherein removing portions of the first conductive material and removing surface portions are performed during a same polishing process.

14. A method for forming a semiconductor device comprising:

forming first gate structures over a semiconductor device substrate, wherein the first

gate structures include a first gate dielectric and a first gate electrode material;

forming an insulating layer over the first gate structures;

removing portions of the insulating layer;

exposing portions of the first gate electrode material;

removing portions of the first gate electrode material from at least one of the first gate structures to form an opening;

filling the opening with a second gate electrode material; and

polishing the second gate electrode material to form a second gate structure over the semiconductor device substrate, wherein the second gate structure operates at a threshold voltage that is different from the first gate structures.

15. The method of claim 14, further comprising:

removing portions of the first gate dielectric after removing portions of the first gate electrode material; and

filling the opening with a second gate dielectric prior to filling the opening with a second gate electrode material.

16. The method of claim 15, wherein the first gate electrode material is different from the second gate electrode material.