Wafer of semiconductor material for fabricating integrated devices, and process for its fabrication

• US 6,171,931 B1
• Filed: 10/06/1998
• Issued: 01/09/2001
• Est. Priority Date: 12/15/1994
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Inventors: Villa, Flavio, Mastromatteo, Ubaldo, Murari, Bruno
• Primary Examiner(s): Dang, Trung
• Application Number:
  US09/167,246
• Time in Patent Office: 826 Days
• Field of Search: 438/455, 438/459, 438/406, 438/404
• US Class Current: 438/455
• CPC Class Codes: H01L 21/02112 characterised by the material of the layer
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02167 the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02175 characterised by the metal H01L21/02197 takes precedence
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02323 introduction of oxygen
• CPC Class Codes: H01L 21/02356 treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
• CPC Class Codes: H01L 21/31662 of silicon in uncombined form
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/76256 using silicon etch back techniques, e.g. BESOI, ELTRAN
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 24/26 Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A wafer of semiconductor material for fabricating integrated devices, including a stack of superimposed layers including first and second monocrystalline silicon layers separated by an intermediate insulating layer made of a material selected from the group comprising silicon carbide, silicon nitride and ceramic materials. An oxide bond layer is provided between the intermediate layer and the second silicon layer. The wafer is fabricated by forming the intermediate insulating layer on the first silicon layer in a heated vacuum chamber; depositing the oxide layer; and superimposing the second silicon layer. When the stack of silicon, insulating material, oxide and silicon layers is heat treated, the oxide reacts so as to bond the insulating layer to the second silicon layer. As a ceramic material beryllium oxide, aluminium nitride, boron nitride and alumina may be used.

Claims

1. A process for fabricating a wafer of semiconductor material comprising the steps of:

forming, on a first silicon layer, an intermediate insulating layer made of a monocrystalline material selected from a group comprising silicon carbide, silicon nitride and ceramic materials; and

bonding a second silicon layer to said insulating layer.

3. A process as claimed in claim 1, wherein said first and second silicon layers are of monocrystalline silicon.

4. A process as claimed in claim 1, wherein said bonding step includes the step of forming a bond layer between said insulating layer and said second silicon layer.

5. A process as claimed in claim 4, wherein said step of forming a bond layer comprises the steps of:

forming a silicon oxide layer on said insulating layer; and

placing said second silicon layer on said silicon oxide layer; and

heat treating said wafer to activate the reaction;

6. A process as claimed in claim 5, wherein said step of forming a silicon oxide layer comprises the step of depositing a TEOS silicon oxide layer on said insulating layer.

7. A process as claimed in claim 5, wherein said step of forming a silicon oxide layer comprises the step of depositing a CVD silicon oxide layer on said insulating layer.

8. A process as claimed in claim 5, wherein said step of forming a silicon oxide layer comprises the step of forming a thermal oxide layer on said insulating layer.

10. A process as claimed in claim 1, wherein said step of forming said insulating layer of silicon carbide comprises the steps of:

heating said first silicon layer;

supplying a gas including a mixture of hydrocarbons and silane; and

activating said gas.

12. A process as claimed in claim 1, wherein said step of forming said insulating layer comprises the step of growing a CVD silicon nitride layer.

13. A process as claimed in claim 1, wherein said step of forming said insulating layer of silicon nitride comprises the steps of:

thermally growing a thermal silicon oxide layer on said first silicon layer;

supplying a gas including a mixture of silane and ammonia; and

activating said gas.

14. A process as claimed claim 5, wherein said bonding step comprises the steps of:

forming a first bonding silicon oxide layer on said insulating layer;

forming a second bonding silicon oxide layer on said second silicon layer;

bonding said first and second boding silicon oxide layers.

15. A process as claimed claim 14, wherein said first bonding silicon oxide layer has a thickness in the range 400-600 Å

.

16. A process as claimed claim 14, wherein said second bonding silicon oxide layer is a native oxide.

2. A process for fabricating a wafer of semiconductor material comprising the steps of:

forming, on a first silicon layer, an intermediate insulating layer made of a monocrystalline material selected from a group comprising silicon carbide, silicon nitride and ceramic materials; and

bonding a second silicon layer to said insulating layer;

wherein said ceramic material is selected from a group comprising beryllium oxide, aluminum nitride, boron nitride and alumina.

9. A process for fabricating a wafer of semiconductor material comprising the steps of:

forming, on a first silicon layer, an intermediate insulating layer made of a material selected from a group comprising silicon carbide, silicon nitride and ceramic materials; and

bonding a second silicon layer to said insulating layer;

wherein said bonding step includes a step of forming a bond layer between said insulating layer and said second silicon layer and a step of depositing a polycrystalline silicon layer on said insulating layer.

11. A process for fabricating a wafer of semiconductor material comprising the steps of:

forming, on a first silicon layer, an intermediate insulating layer made of a material selected from a group comprising silicon carbide, silicon nitride and ceramic materials; and

bonding a second silicon layer to said insulating layer;

wherein said step of forming said insulating layer of silicon carbide comprises the steps of;

growing an amorphous-phase silicon carbide layer; and

recrystallizing said amorphous-phase silicon carbide layer as a monocrystalline silicon carbide layer.

17. A process for fabricating a wafer of semiconductor material comprising the steps of:

forming, on a first silicon layer, an intermediate insulating layer made of a material selected from a group comprising silicon carbide, silicon nitride and ceramic materials; and

bonding a second silicon layer to said insulating layer;

wherein said step of forming said insulating layer comprises the steps of;

forming a sintered insulating layer; and

bonding said sintered insulating layer to said first silicon layer.

18. A process as claimed in claim 17, further comprising the steps of:

after said sintered insulating layer bonding step, polishing said bonded sintered insulating layer; and

forming an oxide bond layer on said sintered insulating layer.

19. A process as claimed in claim 17, wherein the sintered insulating layer is made of silicon nitride.