Integrated circuit varactor having a wide capacitance range

• US 6,172,378 B1
• Filed: 05/03/1999
• Issued: 01/09/2001
• Est. Priority Date: 05/03/1999
• Status: Active Grant

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: Silicon Wave, Inc. (Qorvo, Inc.)
• Inventors: Seefeldt, James Douglas, Seendripu, Kishore V., Hull, Christopher D.
• Primary Examiner(s): Meier, Stephen D.
• Application Number:
  US09/304,457
• Time in Patent Office: 617 Days
• Field of Search: 257/360, 257/291, 257/14, 257/13
• US Class Current: 257/14
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS

Abstract

Integrated circuit varactor structures that include either an P-gate/N-well or N-gate/P-well layer configuration formed on an SOI substrate. The varactor structure is completely electrically isolated from the substrate of the IC by an oxide layer of the SOI substrate and by oxide-filled trenches formed on both sides of the varactor structures. The isolation trenches preferably extend to the oxide layer of the SOI substrate. The P-gate/N-well varactor structure includes N⁺ implant regions formed in an N-well implant layer of the varactor. The N⁺ implant regions comprise the source and the drain of a varactor. A LOCOS layer may be formed over the N-well layer where the P-gate is formed over the LOCOS layer. The P-gate may be formed of polysilicon. The N-gate/P-well varactor structure includes P⁺ implant regions formed in a P-well implant layer of the varactor. The P⁺ implant regions comprise the source and the drain of a varactor. A LOCOS layer may be formed over the P-well layer where the N-gate is formed over the LOCOS layer. The N-gate may be formed of polysilicon. The P-gate/N-well varactor is ideally suited for use as a binary or digitally-controlled varactor because it abruptly changes from a first lower capacitance of C₁ to a second higher capacitance of C₂ as the D.C. control voltage is varied from a first to a second threshold level. In contrast, the N-gate/P-well varactor finds utility as an analog timing varactor of a fully integrated VCO device, for example, because it slowly changes from a first lower capacitance of C₁ to a second higher capacitance of C₂ as the D.C. control voltage is varied from low to high threshold voltage levels.

Claims

1. A semiconductor integrated circuit (IC) device comprising:

a) a substrate;

b) a first insulating layer formed on the substrate;

c) a first semiconductor layer formed on the insulating layer;

d) one of an N-well and P-well implant layer formed in the first semiconductor layer;

e) a first region of one of an N⁺ and a P⁺ implant formed in the one of an N-well and P-well implant layer;

f) a second region of one of an N⁺ and a P⁺ implant formed in the one of an N-well and P-well implant layer;

g) a second insulating layer formed over a selected portion of a surface of the one of an N-well and P-well implant layer;

h) a second semiconductor layer formed over a selected portion of a surface of the second insulating layer, and between the first region and the second region, wherein the second semiconductor layer forms one of a P-gate and an N-gate; and

i) an isolation region extending from the first insulating layer to the second insulating layer and surrounding and electrically isolating the implant layer, the implant regions, and the second semiconductor layer.

2. The IC device according to claim 1, wherein the substrate is a high resistivity substrate.

3. The IC device according to claim 2, wherein the resistivity of the substrate is approximately 1 kohm-cm.

4. The IC device according to claim 3, wherein the first insulating layer comprises one of a silicon oxide and a ceramic insulating material.

5. The IC device according to claim 4, wherein the second insulating layer is formed from one of a local oxidation, a local nitridation, and a covalent bonding of silicon.

6. The IC device according to claim 4, wherein the first semiconductor layer further includes one of an N buried layer and a P buried layer formed adjacent to and above the first insulating layer.

7. The IC device according to claim 6, wherein the first semiconductor layer further includes one of an N collector layer and a P collector layer formed adjacent to and above the one of the N buried layer and the P buried layer.

8. The IC device according to claim 1, wherein the isolation region includes an isolation trench formed in the first semiconductor layer, wherein the trench extends from the first insulating layer to the second insulating layer and surrounds and electrically isolates the implant layer, the implant regions, and the second semiconductor layer.

9. The IC device according to claim 8, wherein the second semiconductor layer includes polysilicon.

10. A semiconductor integrated circuit (IC) device comprising:

a) a substrate;

b) a first insulating layer formed on the substrate;

c) a first semiconductor layer formed on the insulating layer;

d) an N-well implant layer formed in the first semiconductor layer;

e) a first region of an N⁺ implant formed in the N-well implant layer;

f) a second region of an N⁺ implant formed in the N-well implant layer;

g) a second insulating layer form over a selected portion of a surface of the N-well implant layer;

h) a second semiconductor layer formed over a selected portion of the surface of the second insulating layer, and between the first region and the second region, wherein the second semiconductor layer forms a P-gate; and

i) an isolation region extending from the first insulating layer to the second insulating layer and surrounding and electrically isolating the implant layer, the implant regions, and the second semiconductor layer.

11. The IC device according to claim 10, wherein the substrate comprises high resistivity material.

12. The IC device according to claim 11, wherein the resistivity of the substrate comprises approximately 1 kohm-cm.

13. The IC device according to claim 12, wherein the first insulating layer comprises one of a silicon oxide and a ceramic insulating material.

14. The IC device according to claim 13, wherein the second insulating layer is formed from one of a local oxidation, a local nitridation, and a covalent bonding of silicon.

15. The IC device according to claim 13, wherein the first semiconductor layer further includes an N-buried layer formed adjacent to and above the first insulating layer.

16. The IC device according to claim 15, wherein the first semiconductor layer further includes an N collector layer formed adjacent to and above the N-buried layer.

17. The IC device according to claim 10, wherein the isolation region includes an isolation trench formed in the first semiconductor layer that extends from the first insulating layer to the second insulating layer, and wherein the isolation trench surrounds the implant layer, the implant regions, and the second semiconductor layer.

18. The IC device according to claim 17, wherein the second semiconductor layer includes polysilicon.

19. A semiconductor integrated circuit (IC) device comprising:

a) a substrate;

b) a first insulating layer formed on the substrate;

c) a first semiconductor layer formed on the insulating layer;

d) a P-well implant layer formed in the first semiconductor layer;

e) a first region of an P⁺ implant formed in the P-well implant layer;

f) a second region of an P⁺ implant formed in the P-well implant layer;

g) a second insulating layer formed over a selected portion of a surface of the P-well implant layer;

h) a second semiconductor layer formed over a selected portion of a surface of the second insulating layer and between the first region and the second region, wherein the second semiconductor layer forms an N-gate;

i) an isolation region extending from the first insulating layer to the second insulating layer and surrounding and electrically isolating the implant layer, the implant regions, and the second semiconductor layer.

20. The IC device according to claim 19, wherein the substrate comprises high resistivity material.

21. The IC device according to claim 20, wherein the resistivity of the substrate comprises approximately 1 kohm-cm.

22. The IC device according to claim 21, wherein the first insulating layer comprises one of a silicon oxide and a ceramic insulating material.

23. The IC device according to claim 22, wherein the second insulating layer is formed from one of a local oxidation, a local nitridation, and a covalent bonding of silicon.

24. The IC device according to claim 22, wherein the first semiconductor layer further includes a P-buried layer formed adjacent to and above the first insulating layer.

25. The IC device according to claim 24, wherein the first semiconductor layer further includes a P collector layer formed adjacent to and above the P-buried layer.

26. The IC device according to claim 19, wherein the isolation region includes an isolation trench formed in the first semiconductor layer that extends from the first insulating layer to the second insulating layer, and wherein the isolation trench surrounds the implant layer, the implant regions, and the second semiconductor layer.

27. The IC device according to claim 26, wherein the second semiconductor layer includes polysilicon.