Low profile ball grid array package

• US 6,172,419 B1
• Filed: 02/24/1998
• Issued: 01/09/2001
• Est. Priority Date: 02/24/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kinsman, Larry D.
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US09/028,646
• Time in Patent Office: 1,050 Days
• Field of Search: 257/737, 257/738, 257/778, 257/690, 257/701
• US Class Current: 257/737
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85001 involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 2224/85444 Gold (Au) as principal constituent
• CPC Class Codes: H01L 23/043 the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
• CPC Class Codes: H01L 23/053 the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

The present invention is a method and apparatus for a very low profile ball grid array package. A substrate is provided with an aperture. A thin sheet material is secured to the substrate, covering the aperture, so as to form a cavity. A semiconductor die is mounted in the formed cavity on the thin sheet material. The semiconductor die is encapsulated with the thin sheet material supporting it during encapsulation. The use of the thin sheet material to form the cavity is a cost effective way to construct a ball grid array package having a very low profile.

Claims

1. A low profile ball grid array semiconductor package comprising:

a base substrate having a top surface and a bottom surface, with an aperture therein which extends from said top surface to said bottom surface;

a series of conductive traces located on said bottom surface of said base substrate;

a plurality of conductive balls connected to said series of conductive traces;

a thin sheet material secured to said base substrate and covering said aperture such that a cavity is formed, said thin sheet material having a thickness of approximately 0.025 to 0.1 mm; and

a semiconductor element mounted in said cavity.

2. The low profile ball grid array semiconductor package according to claim 1, said thin sheet material further comprising:

a polyimide based material.

3. The low profile ball grid array semiconductor package according to claim 1, said thin sheet material further comprising:

a metal foil based material.

4. The low profile ball grid array semiconductor package according to claim 1 further comprising:

an encapsulant covering at least a portion of said semiconductor element and said base substrate.

5. A low profile ball grid array semiconductor package comprising:

a base substrate having a top surface and a bottom surface, said base substrate having an aperture extending from said top surface to said bottom surface;

a series of conductive traces located on said bottom surface of said base substrate;

a plurality of conductive balls connected to said series of conductive traces;

a thin sheet material thick secured to said top surface of said base substrate and covering said aperture to form a downward facing cavity, said thin sheet material having a thickness of approximately 0.025 to 0.1 mm; and

a semiconductor element mounted in said downward facing cavity.

6. The low profile ball grid array semiconductor package of claim 5, said thin sheet material further comprising:

a polyimide based material.

7. The low profile ball grid array package of claim 5, said thin sheet material further comprising:

a metal foil based material.

8. The low profile ball grid array package of claim 5 further comprising:

an encapsulant covering at least a portion of said semiconductor element and said base substrate.

9. A low profile ball grid array semiconductor package comprising:

an insulating substrate having a top surface and a bottom surface, said insulating substrate having an aperture extending from said top surface to said bottom surface;

a first series of conductive traces located on said top surface of said insulating substrate and a second series of conductive traces located on said bottom surface of said insulating substrate, said first series connected to said second series by via holes in said insulating substrate;

a thin sheet material approximately 0.025 to 0.1 mm thick secured to said bottom surface of said insulating substrate and covering said aperture such that a cavity is formed;

a semiconductor element mounted in said cavity, said semiconductor element having a plurality of bond pads, each of said bond pads associated with an input or an output of said semiconductor element;

a plurality of wire bonds connecting said bond pads of said semiconductor element to said first series of conductive traces;

a plurality of conductive balls connected to said second series of conductive traces; and

an encapsulant covering at least a portion of said semiconductor element and said insulating substrate.

10. The low profile ball grid array semiconductor package of claim 9, said thin sheet material further comprising:

a polyimide based material.

11. The low profile ball grid array package of claim 9, said thin sheet material further comprising:

a metal foil based material.

12. A low profile ball grid array semiconductor package comprising:

an insulating substrate having a top surface and a bottom surface, said insulating substrate having an aperture extending from said top surface to said bottom surface;

a series of conductive traces located on said bottom surface of said insulating substrate;

a thin sheet material thick secured to said top surface of said insulating substrate and covering said aperture such that a downward facing cavity is formed, said thin sheet material having a thickness of approximately 0.025 to 0.1 mm;

a semiconductor element mounted in said downward facing cavity, said semiconductor element having a plurality of bond pads, each of said bond pads associated with an input or an output of said semiconductor element;

a plurality of wire bonds connecting said bond pads of said semiconductor element to said series of conductive traces;

a plurality of conductive balls connected to said series of conductive traces; and

an encapsulant covering at least a portion of said semiconductor element and said insulating substrate.

13. The low profile ball grid array semiconductor package of claim 12, said thin sheet material further comprising:

a polyimide based material.

14. The low profile ball grid array package of claim 12, said thin sheet material further comprising:

a metal foil based material.

15. An integrated circuit comprising:

a plurality of low profile ball grid array semiconductor packages; and

a plurality of leads connecting said plurality of ball grid array semiconductor packages together to form a complete circuit, said low profile ball grid array semiconductor packages further comprising a semiconductor element mounted in a cavity on a thin sheet material approximately 0.025 to 0.1 mm thick.

16. The integrated circuit of claim 15, each of said low profile ball grid array semiconductor packages further comprising:

a base substrate having a top surface and a bottom surface, said base substrate having an aperture extending from said top surface to said bottom surface, said thin sheet material being secured to said bottom surface of said base substrate to cover said aperture and form said cavity, said semiconductor element being mounted in said cavity on said thin sheet material;

a first series of conductive traces located on said top surface of said base substrate and a second series of conductive traces located on said bottom surface of said base substrate, said first series of conductive traces being connected to said second series of conductive traces by via holes in said base substrate;

a plurality of bond pads on said semiconductor element, each of said bond pads associated with an input or output of said semiconductor element;

a plurality of wire bonds connecting said bond pads of said semiconductor element to said first series of conductive traces;

a plurality of conductive balls connected to said second series of conductive traces; and

an encapsulant covering at least a portion of said semiconductor element and said base substrate.

17. The integrated circuit of claim 15, each of said low profile ball grid array package further comprising:

a base substrate having a top surface and a bottom surface, said base substrate having an aperture extending from said top surface to said bottom surface, said thin sheet material being secured to said top surface of said base substrate to cover said aperture and form said cavity in a downward direction, said semiconductor element being mounted in said downward cavity;

a series of conductive traces located on said bottom surface of said base substrate;

a plurality of bond pads on said semiconductor element, each of said bond pads associated with an input or output of said semiconductor element;

a plurality of wire bonds connecting said bond pads of said semiconductor element to said series of conductive traces;

a plurality of conductive balls connected to said series of conductive traces; and

an encapsulant covering at least a portion of said semiconductor element and said base substrate.

18. A device for mounting a semiconductor element comprising:

an insulating substrate, said insulating substrate having a top surface and a bottom surface, with an aperture therein extending from said top surface to said bottom surface;

a series of conductive traces located on said bottom surface of said insulating substrate;

a plurality of conductive balls connected to said series of conductive traces; and

a thin sheet material approximately 0.025 to 0.1 mm thick secured to said bottom surface of said insulating substrate and covering said aperture to form an upwards facing cavity,

wherein said semiconductor element is mounted in said cavity.

19. The device for mounting a semiconductor element according to claim 18, said thin sheet material further comprising:

a polyimide based material.

20. The device for mounting a semiconductor element according to claim 18, said thin sheet material further comprising:

a metal foil based material.

21. A device for mounting a semiconductor element comprising:

an insulating substrate, said insulating substrate having a top surface and a bottom surface, with an aperture therein extending from said top surface to said bottom surface;

a series of conductive traces located on said bottom surface of said insulating substrate;

a plurality of conductive balls connected to said series of conductive traces; and

a thin sheet material approximately 0.025 to 0.1 mm thick secured to said top surface of said insulating substrate and covering said aperture to form a downwards facing cavity,

wherein said semiconductor element is mounted in said downwards facing cavity.

22. The device for mounting a semiconductor element according to claim 21, said thin sheet material further comprising:

a polyimide based material.

23. The device for mounting a semiconductor element according to claim 21, said thin sheet material further comprising:

a metal foil based material.

24. A printed circuit board comprising:

a plurality of low profile ball grid array semiconductor packages; and

a plurality of leads connecting said plurality of ball grid array semiconductor packages together to form a complete circuit, said low profile ball grid array semiconductor packages further comprising a semiconductor element mounted in a cavity on a thin sheet material, said thin sheet material having a thickness of approximately 0.025 to 0.1 mm.

25. The printed circuit board according to claim 24, each of said low profile ball grid array semiconductor packages further comprising:

a base substrate having a top surface and a bottom surface, said base substrate having an aperture extending from said top surface to said bottom surface, said thin sheet material being secured to said bottom surface of said base substrate to cover said aperture and form said cavity, said semiconductor element being mounted in said cavity on said thin sheet material;

a first series of conductive traces located on said top surface of said base substrate and a second series of conductive traces located on said bottom surface of said base substrate, said first series of conductive traces being connected to said second series of conductive traces by via holes in said base substrate;

a plurality of bond pads on said semiconductor element, each of said bond pads associated with an input or output of said semiconductor element;

a plurality of wire bonds connecting said bond pads of said semiconductor element to said first series of conductive traces;

a plurality of conductive balls connected to said second series of conductive traces; and

an encapsulant covering at least a portion of said semiconductor element and said base substrate.

26. The printed circuit board according to claim 24, each of said low profile ball grid array semiconductor packages further comprising:

a base substrate having a top surface and a bottom surface, said base substrate having an aperture extending from said top surface to said bottom surface, said thin sheet material being secured to top surface of said base substrate to cover said aperture and form said cavity in a downward direction, said semiconductor element being mounted in said cavity;

a series of conductive traces located on said bottom surface of said base substrate;

a plurality of bond pads on said semiconductor element, each of said bond pads associated with an input or output of said semiconductor element;

a plurality of wire bonds connecting said bond pads of said semiconductor element to said series of conductive traces;

a plurality of conductive balls connected to said series of conductive traces; and

an encapsulant covering at least a portion of said semiconductor element and said base substrate.