Power supply monitoring integrated circuit device and battery pack

• US 6,172,485 B1
• Filed: 07/22/1999
• Issued: 01/09/2001
• Est. Priority Date: 01/30/1997
• Status: Expired due to Term

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Fujita, Hiroyuki, Inoue, Koichi
• Primary Examiner(s): Wong, Peter S.
• Assistant Examiner(s): TOATLEY, GREGORY J
• Application Number:
  US09/341,686
• Time in Patent Office: 537 Days
• Field of Search: 320/136, 320/134, 320/118, 320/120, 320/162, 324/433
• US Class Current: 320/136
• CPC Class Codes: G01R 19/16542 for batteries charge condition monitoring in G01R31/36
• CPC Class Codes: H02J 7/0014 Circuits for equalisation of charge between batteries
• CPC Class Codes: H02J 7/00302 Overcharge protection
• CPC Class Codes: H02J 7/00304 Overcurrent protection
• CPC Class Codes: H02J 7/00306 Overdischarge protection
• CPC Class Codes: H02J 7/0048 Detection of remaining charge capacity or state of charge [SOC]

Abstract

A power supply controlling integrated circuit device have detection input terminals for receiving the voltages of a plurality of cells and a plurality of comparing means for comparing the voltages of the individual cells with a predetermined reference voltage. To control discharging or charging of the cells in accordance with the outputs of the comparing means, a mode terminal is provided for receiving a signal for designating the number of cells. Also provided are a first circuit that can forcibly bring part of the comparing means into a predetermined output state in accordance with the signal received at the mode terminal and a second circuit for excluding from monitoring the outputs of those comparing means which have been brought into the predetermined output state. This enables the power supply monitoring integrated circuit device to control different numbers of cells without requiring any separately-mounted component or the like.

Claims

1. A power supply monitoring integrated circuit device, having input terminals for receiving voltages of a plurality of cells and a plurality of comparing means for comparing the voltages of the individual cells with a predetermined reference voltage, for controlling discharging or charging of the cells in accordance with outputs of the comparing means, characterized by being provided with:

a mode terminal for receiving a signal for designating a number of cells that are controlled by the power supply monitoring integrated circuit device;

a first circuit that can forcibly bring part of the comparing means into a predetermined output state in accordance with the signal received at the mode terminal; and

a second circuit for excluding from monitoring the outputs of those comparing means which have been brought into the predetermined output state.

2. A power supply monitoring integrated circuit device as claimed in claim 1, characterized in that:

the reference voltage is an overdischarge voltage;

the comparing means each output a first level when the voltage of the corresponding cell is higher than the overdischarge voltage, and output a second level when the voltage of the corresponding cell is lower than the overdischarge voltage; and

the second circuit for achieving exclusion from monitoring performs an AND operation on the outputs of the comparing means by means of an AND circuit, and forces part of the comparing means to output a first level in accordance with the signal received at the mode terminal by means of the first circuit for forcibly bringing about a predetermined output state.

3. A power supply monitoring integrated circuit device as claimed in claim 1, characterized in that:

the first circuit is an OR circuit that is connected to a particular comparing means and to the mode terminal so as to receive an output of the particular comparing means and the signal received at the mode terminal; and

the second circuit is an AND circuit that receives an output of the OR circuit and outputs of the comparing means other than the particular comparing means.

4. A battery pack having a cell, a switching device connected in series with the cell, and a power supply monitoring integrated circuit device, the switching device being turned on and off in accordance with a result of monitoring by the power supply monitoring integrated circuit device, wherein the power supply monitoring integrated circuit device comprises:

input terminals for receiving voltages of a plurality of cells;

a plurality of comparing means for comparing the voltages of the individual cells with a predetermined reference voltage;

a mode terminal for receiving a signal for designating a number of cells that are controlled by the power supply monitoring integrated circuit device;

a first circuit that can forcibly bring part of the comparing means into a predetermined output state in accordance with the signal received at the mode terminal; and

a second circuit for excluding from monitoring the outputs of those comparing means which have been brought into the predetermined output state.

5. A power supply monitoring integrated circuit device as claimed in claim 4, characterized in that:

the reference voltage is an overdischarge voltage;

the comparing means each output a first level when the voltage of the corresponding cell is higher than the overdischarge voltage, and output a second level when the voltage of the corresponding cell is lower than the overdischarge voltage; and

the second circuit for achieving exclusion from monitoring performs an AND operation on the outputs of the comparing means by means of an AND circuit, and forces part of the comparing means to output a first level in accordance with the signal received at the mode terminal by means of the first circuit for forcibly bringing about a predetermined output state.

6. A power supply monitoring integrated circuit device as claimed in claim 4, characterized in that:

the first circuit is an OR circuit that is connected to a particular comparing means and to the mode terminal so as to receive an output of the particular comparing means and the signal received at the mode terminal; and

the second circuit is an AND circuit that receives an output of the OR circuit and outputs of the comparing means other than the particular comparing means.