Cryogenically-cooled switching circuit

• US 6,172,550 B1
• Filed: 08/16/1996
• Issued: 01/09/2001
• Est. Priority Date: 08/16/1996
• Status: Expired due to Fees

• Current Assignee: American Superconductor Corporation
• Original Assignee: American Superconductor Corporation
• Inventors: Mueller, Otward M., Gold, Calman
• Primary Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US08/699,005
• Time in Patent Office: 1,607 Days
• Field of Search: 327/366-373, 327/110, 363/17, 363/19, 363/75, 363/78, 363/84, 363/98, 363/132, 363/141
• US Class Current: 327/366
• CPC Class Codes: H03K 17/92 by the use, as active elements, of superconductive devices
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption

Abstract

An electronic power conversion circuit includes cryogenically cooled MOSFET power switching devices arranged in a switch-mode configuration and responsive to control signals for reducing capacitive discharge and commutation losses in the circuit by controlling the period between switch-on and switch-off time (i.e., “deadtime”) of the MOSFET devices. When one of the MOSFET devices of the circuit is switched off, the opposing MOSFET, after the short deadtime period, is switched on to serve as a commutating device rather, than the opposing MOSFET'"'"'s intrinsic drain-source diode. The power conversion circuit may include a half-bridge circuit or combinations thereof.

Claims

1. A power conversion system comprising:

a switching circuit having an input terminal for supplying power to said circuit and an output terminal coupled to a load which receives power from said circuit, said circuit comprising;

cryogenically cooled first and second switching devices, each switching device comprising an intrinsic drain-to-source commutating diode capable of conveying an inductive current component from the load;

a controller, which controls a deadtime period between switching of the first switching device and the second switching device, the controller providing a first control signal to turn-on the first switching device in a first time interval following turn-off of the second switching device, such that an inductive current component flows through the first switching device rather than through the intrinsic drain-to-source diode associated with the first switching device, said controller including a sensing circuit for sensing said inductive current component for generating said first control signal; and

a refrigeration unit for cryogenically cooling at least said switching devices.

2. The power conversion system of claim 1 further comprising an inductor filter connected to the output terminal, and wherein said refrigeration unit cryogenically cools said inductor filter.

3. The power conversion system of claim 1 wherein said switching devices are MOSFETs.

4. The power conversion of claim 1 wherein the controller includes:

sample-and-hold circuitry which samples the inductive current component with the sensing circuit; and

a clock oscillator, responsive to a control signal from the sample-and-hold circuitry, for generating a feedback signal;

a timing generator which, in response to a pulsewidth modulated signal and the feedback signal, generates the first control signal and a second control signal.

5. A method of reducing the switching losses of a cryogenically-cooled switching circuit comprising first and second switching devices connected to a load circuit having an inductive component, each of said switching devices comprising an intrinsic drain-to-source commutating diode, said method comprising the steps of:

controlling a deadtime period between switching of the first switching device and the second switching device by;

applying to the first switching device when in a turned-on state, a first control signal to turn-off said first switching device;

applying, in the deadtime period following turn-off of said first switching device, a second control signal to turn-on said second switching device to convey an inductive current component from the load circuit through said second switching device rather than through said intrinsic drain-to-source commutating diode associated with said second switching device; and

generating said second control signal in response to a sensed value of the inductive current component.

6. The method of claim 5 wherein said step of applying a second control signal occurs at a time when a voltage across the second switching device is substantially zero.

7. The method of claim 5 further comprising the step of discharging a parasitic capacitance of said second switching device during the commutation interval.

8. A switching circuit having an input terminal for supplying power to said circuit and an output terminal coupled to a load receiving power from said circuit, comprising:

a pair of switching devices including a cryogenically cooled first switching device and a cryogenically cooled second switching device, each switching device comprising an intrinsic drain-to-source commutating diode capable of conveying an inductive current component from the load; and

a controller, which controls a deadtime period between switching of the first switching device and the second switching device, the controller providing a first control signal to turn-on the first switching device in a first deadtime period following turn-off of the second switching device, such that an inductive current component flows through the first switching device rather than through the intrinsic drain-to-source diode associated with the first switching device, said controller including a sensing circuit for sensing said inductive current component for generating said first control signal, the controller including

sample-and-hold circuitry which samples the inductive current component with the sensing circuit;

a clock oscillator, responsive to a control signal from the sample-and-hold circuitry, for generating a feedback signal; and

a timing generator which, in response to a pulsewidth modulated signal and the feedback signal, generates the first control signal and a second control signal.

9. A half-bridge switching circuit having an input terminal for supplying power to said circuit and an output terminal coupled to a load receiving power from said circuit, comprising:

a pair of switching devices including a cryogenically cooled first switching device and a cryogenically cooled second switching device, the pair of switching devices being configured as a half-bridge circuit, each switching device comprising an intrinsic drain-to-source commutating diode capable of conveying an inductive current component from the load; and

a controller, which controls a deadtime period between switching of the first switching device and the second switching device, the controller providing a first control signal to turn-on the first switching device in a first deadtime period following turn-off of the second switching device, such that an inductive current component flows through the first switching device rather than through the intrinsic drain-to-source diode associated with the first switching device, said controller including a sensing circuit for sensing said inductive current component for generating said first control signal.

10. The half-bridge switching circuit of claim 9 wherein turn-on of said first switching device during the first deadtime period occurs at a time when a voltage across the first switching device is substantially zero.

11. The half-bridge switching circuit of claim 9 wherein the first and second control signals are pulse width modulated control signals having a duty cycle in the range of 10% to 90%.

12. The half-bridge switching circuit of claim 9 wherein the first and second control signals are pulse width modulated control signals having a duty cycle in the range of about 30% to about 70%.

13. The half-bridge switching circuit of claim 9 wherein the pair of switching devices provide at least one hundred watts of power to the load.

14. The half-bridge switching circuit of claim 9 wherein said switching devices are bi-dirctional devices.

15. The half-bridge switching circuit of claim 14 wherein said bi-directional devices are MOSFET devices.

16. A full-bridge switching circuit having an input terminal for supplying power to said circuit and an output terminal coupled to a load receiving power from said circuit, comprising:

a first pair of switching devices including a cryogenically cooled first switching device and a cryogenically cooled second switching device, the first pair of switching devices being configured as a half-bridge circuit, each switching device including an intrinsic drain-to-source commutating diode capable of conveying an inductive current component from the load;

a second pair of switching devices including a cryogenically cooled third switching device and a cryogenically cooled fourth switching device, the second pair of switching devices being configured as a half-bridge circuit, each switching device including an intrinsic drain-to-source commutating diode capable of conveying the inductive current component from the load, the first, second, third and fourth switching devices being configured as a full-bridge circuit; and

a controller controlling a deadtime period between switching of the first, second, third and fourth switching devices, the controller providing a first control signal to turn-on the first switching device and the third switching device in a first deadtime period following turn-off of the second switching device and the fourth switching device, such that an inductive current component flows through the first switching device and the third switching device rather than through the intrinsic drain-to-source diode associated with the first switching device and the third switching device.

17. The full-bridge switching circuit of claim 16 wherein turn-on of said first switching device and said third switching device in the first deadtime period occurs at a time when voltages across the first switching device and the third switching device are substantially zero.

18. The full-bridge switching circuit of claim 16 wherein the first and second control signals are pulse width modulated control signals having a duty cycle in the range of 10% to 90%.

19. The full-bridge switching circuit of claim 16 wherein the first and second control signals are pulse width modulated control signals having a duty cycle in the range of about 30% to about 70%.

20. The full-bridge switching circuit of claim 16 wherein the two pairs of switching devices provide at least one hundred watts of power to the load.

21. The full-bridge switching circuit of claim 16 wherein said switching devices are bi-dirctional devices.

22. The full-bridge switching circuit of claim 21 wherein said bidirectional devices are MOSFET devices.

23. A polyphase switching circuit having an input terminal for supplying power to said circuit and an output terminal coupled to a load receiving power from said circuit, comprising:

a plurality of pairs of switching devices configured as a polyphase switching circuit having an input terminal, each of the pair of switching devices having an intrinsic drain-to-source commutating diode capable of conveying the inductive current component from the load, said polyphase switching circuit having a set of terminals for receiving a plurality of alternating current signals having a differential phase shift relationship with respect to each other,

a controller controlling a deadtime period between switching of the switching devices, the controller providing a first control signal to turn-on a first one of the pair of switching devices in a first deadtime period following turn-off of a second one of the pair of switching devices, such that an inductive current component flows through the first one of the pair of switching devices rather than through the intrinsic drain-to-source diode associated with the first one of the switching devices.

24. The polyphase switching circuit of claim 23 wherein turn-on of said first switching device in the first deadtime period occurs at a time when a voltage across the first switching device is substantially zero.

25. The polyphase switching circuit of claim 23 wherein the first and second control signals are pulse width modulated control signals having a duty cycle in the range of 10% to 90%.

26. The polyphase switching circuit of claim 23 wherein the first and second control signals are pulse width modulated control signals having a duty cycle in the range of about 30% to about 70%.

27. The polyphase switching circuit of claim 23 wherein the plurality of pairs of switching devices provide at least one hundred watts of power to the load.

28. The polyphase switching circuit of claim 23 wherein said switching devices are bi-dirctional devices.

29. The polyphase switching circuit of claim 28 wherein said bi-directional devices are MOSFET devices.