Low power driving method for reducing non-display area of TFT-LCD

• US 6,172,661 B1
• Filed: 03/02/1999
• Issued: 01/09/2001
• Est. Priority Date: 07/08/1994
• Status: Expired due to Term

• Current Assignee: Panasonic Liquid Crystal Display Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Hitachi, Ltd.
• Inventors: Imajo, Yoshihiro, Hasegawa, Kaoru, Kondo, Hironori, Igarashi, Youichi
• Primary Examiner(s): NGUYEN, CHANH DUY
• Application Number:
  US09/260,554
• Time in Patent Office: 679 Days
• Field of Search: 345/87, 345/89, 345/92, 345/94, 345/95, 345/52, 345/50, 349/33, 349/34, 349/42
• US Class Current: 345/89
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2330/02 Details of power systems and of start or stop of display operation
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers

Abstract

A liquid crystal display device includes a liquid crystal display panel in which pixels are arranged in rows and columns. Each of the pixels includes a pixel electrode, and a thin-film transistor having a gate electrode and a drain electrode. Gate signal lines arranged in the rows are connected to the gate electrodes of the thin-film transistors. Drain signal lines arranged in the columns are connected to the drain electrodes of the thin-film transistors. The liquid crystal display device further includes a gate drive circuit for driving the gate signal lines, and a drain drive circuit for driving the drain signal lines. The drain drive circuit receives a plurality of grey-scale reference voltages from an external circuit, interpolates a plurality of intermediate voltages between each pair of adjacent ones of the grey-scale reference voltages, selects voltages from the grey-scale reference voltages and the intermediate voltages, and applies the selected voltages to the drain signal lines. V0 is a grey-scale reference voltage corresponding to a minimum grey-scale level, Vm is a grey-scale reference voltage corresponding to a maximum grey-scale level, and Vi is a grey-scale reference voltage that is nearest to a voltage level (Vm+V0)/2. A number of intermediate voltages interpolated between V(i−1) and Vi is different from both a number of intermediate voltages interpolated between V0 and V1, and a number of intermediate voltages interpolated between V(m−1) and Vm.

Claims

1. A TFT liquid crystal display comprising:

a TFT liquid crystal display panel including

an array of pixels including a thin-film transistor and a pixel electrode arranged in a matrix,

a common electrode,

a liquid crystal provided between the array of the pixel electrodes and the common electrode,

a plurality of gate signal lines arranged in rows and connected with gate electrodes of the thin-film transistors in rows, and

a plurality of drain signal lines arranged in columns and connected with drain electrodes of the thin-film transistors in columns;

a gate drive circuit for driving the plurality of gate signal lines of the TFT liquid crystal display panel;

a drain drive circuit for driving the plurality of drain signal lines of the TFT liquid crystal display panel;

a common drive circuit for driving the common electrode;

a grey-scale reference voltage generation circuit; and

a display controller for controlling the circuits in response to control signals and display data from a computer unit;

wherein the drain drive circuit generates intermediate voltages between a plurality of grey-scale reference voltages being generated from the grey-scale reference voltage generation circuit, and the intermediate voltages and the grey-scale reference voltages are applied to the drain signal lines to provide multiple grey-scale display;

wherein the grey-scale reference voltage generation circuit generates a plurality of the grey-scale reference voltages such that the potential difference between the grey-scale reference voltages in a range of service voltage where an applied voltage-transmission factor characteristic of liquid crystal is non-linear is smaller than the potential difference between the grey-scale reference voltages in a range of service voltage where the applied voltage-transmission factor characteristic is relatively linear; and

wherein the number of intermediate voltages generated by the drain drive circuit from the grey-scale reference voltages in the service voltage range where the applied voltage-transmission factor characteristic of liquid crystal is non-linear is smaller than the number of intermediate voltages generated from the grey-scale reference voltages in the service voltage range where the applied voltage-transmission factor characteristic of the liquid crystal is relatively linear.

2. A TFT liquid crystal display according to claim 1, further comprising:

a gate driver board on which the gate drive circuit is mounted;

a drain driver board on which the drain drive circuit is mounted;

a power supply board on which the common drive circuit and a power supply circuit are mounted; and

an interface board on which the display controller is mounted;

wherein the gate driver board, the drain driver board, the power supply board, and the interface board are arranged outside the TFT liquid crystal display panel; and

wherein the drain driver board is installed at only one side of the TFT liquid crystal display panel perpendicular to the side where the gate driver board is installed.

3. A TFT liquid crystal display according to claim 2, wherein the display controller makes an amount of output display data, which is based on an amount of input display data, equal to the amount of input data for the drain driver board.

4. A TFT liquid crystal display according to claim 3, wherein a clock signal to be sent from the display controller to the drain drive circuits is divided into a plurality of clock signals, and the divided clock signals are each transmitted to the drain drive circuits.

5. A TFT liquid crystal display comprising:

a TFT liquid crystal display panel including

an array of pixels including a thin-film transistor and a pixel electrode arranged in a matrix,

a common electrode,

a liquid crystal provided between the array of pixel electrodes and the common electrode,

a plurality of gate signal lines arranged in rows and connected with gate electrodes of the thin-film transistors in rows, and

a plurality of drain signal lines arranged in columns and connected with drain electrodes of the thin-film transistors in columns;

a gate drive circuit for driving the plurality of gate signal lines of the TFT liquid crystal display panel;

a drain drive circuit for driving the plurality of drain signal lines of the TFT liquid crystal display panel;

a common drive circuit for driving the common electrode; and

a display controller for controlling the circuits in response to control signals and display data from a computer unit;

wherein the TFT liquid crystal display panel further includes at least one of;

(a) a trapezoidal AC drive voltage from the common circuit being applied to the common electrode to AC-drive the common electrode;

(b) the array of pixels including the thin-film transistor, the pixel electrode, and a holding capacitance arranged in the matrix,

wherein an AC drive voltage from the common drive circuit is applied to the common electrode to AC-drive the common electrode,

wherein the holding capacitance is provided between the pixel electrode and the signal lines being adjacent to the pixel electrode,

wherein the gate drive circuit selects a gate-on voltage or a gate-off voltage which is lower than the gate-on voltage and drives the gate signal lines, and

wherein the gate-off voltage has a same phase and a same amplitude as the AC drive voltage being applied to the common electrode; and

(c) a grey-scale reference voltage generation circuit.

6. A TFT liquid crystal display according to claim 5, wherein at least (c) is provided;

and

wherein the drain drive circuit generates intermediate voltages between a plurality of grey-scale reference voltages being generated from the grey-scale reference voltage generation circuit, and the intermediate voltage and the grey-scale reference voltages are applied to the drain signal lines to provide multiple grey-scale display;

wherein the grey-scale reference voltage generation circuit generates a plurality of the grey-scale reference voltages such that the potential difference between the grey-scale reference voltages in a range of service voltage where an applied voltage-transmission factor characteristic of liquid crystal is non-linear is smaller than the potential difference between the grey-scale reference voltages in a range of service voltage where the applied voltage-transmission factor characteristic is relatively linear; and

wherein the number of intermediate voltages generated by the drain drive circuit from the grey-scale reference voltages in the service voltage range where the applied voltage-transmission factor characteristic of liquid crystal is non-linear is smaller than the number of intermediate voltages generated from the grey-scale reference voltages in the service voltage range where the applied voltage-transmission factor characteristic of the liquid crystal is relatively linear.

7. A TFT liquid crystal display according to claim 6, wherein (a) and (b) are provided.

8. A liquid crystal display device comprising:

a liquid crystal display panel including

a plurality of pixels arranged in rows and columns, each of the pixels including a thin-film transistor and a pixel electrode, the thin-film transistor having a gate electrode and a drain electrode,

a plurality of gate signal lines arranged in rows and connected to the gate electrodes of the thin-film transistors in respective ones of the rows of pixels, and

a plurality of drain signal lines arranged in columns and connected to the drain electrodes of the thin-film transistors in respective ones of the columns of pixels;

a gate drive circuit for driving the gate signal lines; and

a drain drive circuit for driving the drain signal lines;

wherein the drain drive circuit receives a plurality of grey-scale reference voltages from an external circuit, interpolates a plurality of intermediate voltages between each pair of adjacent ones of the grey-scale reference voltages, selects voltages from the grey-scale reference voltages and the intermediate voltages, and applies the selected voltages to the drain signal lines;

wherein V0 is a grey-scale reference voltage corresponding to a minimum grey-scale level, Vm is a grey-scale reference voltage corresponding to a maximum grey-scale level, and Vi is a grey-scale reference voltage that is nearest to a voltage level (Vm+V0)/2; and

wherein a number of intermediate voltages interpolated between V(i−

1) and Vi is different from both a number of intermediate voltages interpolated between V0 and V1, and a number of intermediate voltages interpolated between V(m−

1) and Vm.