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Memory device and video image processing apparatus using the same

  • US 6,172,687 B1
  • Filed: 03/19/1998
  • Issued: 01/09/2001
  • Est. Priority Date: 04/01/1997
  • Status: Expired due to Fees
First Claim
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1. A memory device comprising:

  • m memory array banks, each including row and column address decoders;

    a first circuit for receiving one address and generating m row addresses and n column addresses by shifting the one address by a predetermined value for each of the m row and n column addresses;

    a second circuit for inputting each of the generated m row and n column addresses to the corresponding row and column address decoders of the m memory array banks;

    the m memory array banks outputting m×

    n data read out simultaneously by the generated m row and n column addresses; and

    a third circuit for calculating and outputting one output signal from the read-out m×

    n data according to a predetermined calculation formula.

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