Memory device and video image processing apparatus using the same

• US 6,172,687 B1
• Filed: 03/19/1998
• Issued: 01/09/2001
• Est. Priority Date: 04/01/1997
• Status: Expired due to Fees

• Current Assignee: Sega Enterprises LTD. (SEGA Sammy Holdings Inc.)
• Original Assignee: Sega Enterprises LTD. (SEGA Sammy Holdings Inc.)
• Inventors: Yagi, Hiroshi, Yasui, Keisuke, Kitamura, Kenya
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US09/044,165
• Time in Patent Office: 1,027 Days
• Field of Search: 345/430, 345/507-510, 345/513, 345/515, 345/516, 345/517, 711/1, 711/5
• US Class Current: 345/564
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence

Abstract

A memory device in which a plurality of data can be read out by giving one address and a plurality of data can be read out without adding more address lines is provided, and therefore, the circuit integration is not degraded. The memory device includes: m memory array banks, each including row and column address decoders; a first circuit for receiving one address and generating m row addresses and n column addresses by shifting the one address by a predetermined value for each of the m row and n column addresses; and a second circuit for inputting each of the generated m row and n column addresses to the corresponding row and column address decoders of the m memory array banks.

Claims

1. A memory device comprising:

m memory array banks, each including row and column address decoders;

a first circuit for receiving one address and generating m row addresses and n column addresses by shifting the one address by a predetermined value for each of the m row and n column addresses;

a second circuit for inputting each of the generated m row and n column addresses to the corresponding row and column address decoders of the m memory array banks;

the m memory array banks outputting m×

n data read out simultaneously by the generated m row and n column addresses; and

a third circuit for calculating and outputting one output signal from the read-out m×

n data according to a predetermined calculation formula.

2. The memory device according to claim 1,

wherein the one address includes row and column addresses, said first circuit shifts each of the row and column addresses of said one address by a predetermined value to generate the m row and n column addresses, and said second circuit inputs the generated m row addresses to said corresponding row address decoders of said m memory array banks, and inputs said generated n column addresses commonly to said column address decoders corresponding to said m memory array banks.

3. The memory device according to claim 1,

wherein the m and n are 2, and the one address is corresponding to a X and Y coordinate for specifying a position where one texture data is stored on a texture map of a video image processing apparatus.

4. A video image processing apparatus for forming an object positioned in a virtual three-dimensional space with a plurality of polygons and displaying on a display device, comprising:

a memory device storing texture data on a plurality of coordinate positions specified by X and Y axes; and

a circuit for determining pixel data to be displayed according to the texture data read out from said memory device on each of pixels forming each of said plurality of polygons,

wherein said memory device includes;

m memory array banks respectively including row and column address decoders,

a first circuit for receiving one coordinate address specified by X and Y axes which specify texture data and generating multiple addresses by shifting said one coordinate address by a predetermined value,

a second circuit for inputting each of said generated multiple addresses to corresponding one of the address decoders of said multiple memory array banks, and outputting plural texture data simultaneously, and

a third circuit for calculating and outputting one output signal from read-out plural texture data according to a predetermined calculation formula.

5. The video image processing apparatus according to claim 4, wherein the m memory array banks include two memory array banks, and the second circuit outputs two addresses.

6. The video image processing apparatus according to claim 4,

wherein the row address in each of the two memory array banks is corresponding to either an odd numbered address or an even numbered address of Y coordinate on the texture map.

7. The video image processing apparatus according to claim 4, wherein the determining circuit determines one pixel data to be displayed by combining multiple texture data read out from the m memory array banks.

8. The video image processing apparatus according to claim 4, wherein the determing circuit determines one pixel data to be displayed according to area assigned to one pixel in the multiple texture data.