Non-volatile magnetic random access memory

• US 6,172,902 B1
• Filed: 08/13/1999
• Issued: 01/09/2001
• Est. Priority Date: 08/12/1998
• Status: Expired due to Term

• Current Assignee: Ecole polytechnique fãdãrale de lausanne epfl (Schweizerische Eidgenossenschaft)
• Original Assignee: Ecole polytechnique fãdãrale de lausanne epfl (Schweizerische Eidgenossenschaft)
• Inventors: Gilbert, Scott E., Wegrowe, Jean-Eric, Ansermet, Jean-Philippe
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/376,714
• Time in Patent Office: 515 Days
• Field of Search: 365/158, 365/129, 365/171, 365/159
• US Class Current: 365/158
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 2213/81 Array wherein the array conductors, e.g. word lines, bit lines, are made of nanowires
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices

Abstract

A non-volatile random access memory (NVRAM) of the type with magnetoresistive memory elements (1) connected by sets of non-intersecting conductor sense lines (3, 4) which define the address of each memory element (1) and are connectable to a magnetic write/read recording unit. The memory elements are a plurality of magnetoresistive submicron dots or wires (1) embedded in a membrane (2) through which the submicron dots or wires extend. The sets of non-intersecting conductor sense lines (3, 4) are connected to the opposite ends of the submicron dots or wires (1) on opposite sides of the membrane. Each magnetoresistive submicron dot or wire (1) is composed of ferromagnetic material or a combination of ferromagnetic and non-ferromagnetic materials having at least two magnetic states (“0”; “1”), writeable by passing at an appropriate external field a writing current pulse (i_w) in its conductor lines (3, 4, 5) sufficient to switch its magnetic states and readable by passing a an AC or DC current (i_r) in its conductor lines below the level for switching its magnetic states.

Claims

1. A non-volatile random access memory comprising a plurality of magnetoresistive memory elements connected by sets of non-intersecting conductor sense lines, the non-intersecting conductor sense lines defining the address of each memory element and being connectable to a magnetic write/read recording unit for writing and reading the magnetic state (“

0”

, “

1”

) of each memory element by passing current in its conductor sense lines;

wherein the memory elements are a plurality of magnetoresistive submicron dots or wires embedded in a membrane through which the submicron dots or wires extend, the sets of non-intersecting conductor sense lines being connected to the opposite ends of the submicron dots or wires on opposite sides of the membrane;

each magnetoresistive submicron dot or wire being composed of ferromagnetic material or a combination of ferromagnetic and non-ferromagnetic materials having at least two magnetic states (“

0”

;

“

1”

), writeable and readable absent an induced magnetic field therein by passing there through an electric current, writeable by passing a writing current pulse in its conductor lines sufficient to switch its magnetic states and readable by passing a current in its conductor lines below the level for switching its magnetic states.

2. The random access memory of claim 1, wherein the submicron dots or wires are composed of ferromagnetic material or of ferromagnetic/non-ferromagnetic metal/ferromagnetic multilayers or a ferromagnetic/dielectric/ferromagnetic junction.

3. The random access memory of claim 1, wherein the submicron dots or wires have a diameter from 10 to 100 nm and a length from 200 to 10,000 nm.

4. The random access memory of claim 1, comprising up to 10⁹ submicron dots or wires per cm² of the membrane.

5. The random access memory of claim 1, wherein the membrane is bonded to or integral with a silicon wafer substrate including integrated circuitry for processing the reading and writing currents.

6. The random access memory of claim 5, wherein the integrated circuitry comprises one integrated circuit element for each memory element comprising a submicron dot or wire.

7. The random access memory of claim 1, wherein the membrane is a track-etched polymer membrane, a porous aluminum oxide membrane, or a porous silicon oxide membrane.

8. The random access memory of claim 1, wherein a ferromagnetic or anti-ferromagnetic layer is provided on the top or bottom of the membrane in contact with the dot or wire to induce a bias exchange field for switching the memory element at weak applied field.

9. The random access memory of claim 1, wherein a ferromagnetic layer is provided on the top or bottom of the membrane and separated from the dot or wire by a thin layer of non-ferromagnetic material, to polarize the conduction electrons and amplify the action of the writing current.

10. A method of producing the random access memory of claim 1, wherein nickel or other ferromagnetic elements or alloys possessing adequate magnetoresistive characteristics are deposited into the pores of a porous membrane template using a layer of resist having a predefined pattern of apertures corresponding to the memory elements each comprising a submicron dot or wire.

11. A data storage device comprising a non-volatile random access memory according to claim 1.

12. A method of writing and reading data in a random access memory according to claim 1, wherein the writing comprises supplying current pulses to change the magnetic state of the memory elements which each comprise a submicron dot or wire, and the reading comprises passing a lower AC or DC current to determine the resistance of the memory elements.