Unified erase method in flash EEPROM

• US 6,172,915 B1
• Filed: 09/30/1999
• Issued: 01/09/2001
• Est. Priority Date: 09/30/1999
• Status: Expired due to Term

• Current Assignee: Esigma Technology Corporation Limited
• Original Assignee: Eon Silicon Devices, Inc.
• Inventors: Yu, James C., Anthony, Jeffrey W., Tang, Yuan
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US09/408,705
• Time in Patent Office: 467 Days
• Field of Search: 365/185.29, 365/185.18, 365/185.19, 365/185.11, 365/185.22, 365/218
• US Class Current: 365/185.29
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A unified erase method used in an array of flash EEPROM memory cells arranged in a plurality of sectors for performing either a single-sector, multiple-sector, or all-sector erasing operation with a reduced amount of total erase time and a uniform V_T distribution as good as that of a single-sector erase operation is provided. An erase-verify operation is performed sequentially on the plurality of sectors from a first sector to a last sector beginning with a first address of each sector if its corresponding erase-on signal is not turned OFF. The current address of each sector is stored at a point where the erase-verify operation failed. An erase pulse is applied only to all sectors simultaneously that have not passed the erase-verify operation. The erase-verify operation is then repeated beginning at the current address stored. The erasing operation is terminated when the erase-on signal has been turned OFF in all sectors in the plurality of sectors.

Claims

1. A unified erase method used in an array of flash EEPROM memory cells arranged in a plurality of sectors for performing either a single-sector, multiple-sector, or all-sector erasing operation with a reduced amount of total erase time, said erase method comprising the steps of:

turning an erase-signal ON in only certain ones of said plurality of sectors which are required to be erased;

programming initially all bytes in said certain ones of said plurality of sectors which are required to be erased;

setting current address in said certain ones of said plurality of sectors which are required to be erased to a first address;

(a) determining whether a first sector of said plurality of sectors has its erase-on signal turned OFF;

(b) bypassing said first sector if said erase-on signal is turned OFF and proceeding to a second sector of said plurality of sectors;

(c) determining whether the current address has been erased if said erase-on signal is not turned OFF;

(d) proceeding to the second sector of said plurality of sectors if the current address has not been erased and storing in an address register the current address;

(e) determining whether the current address is the last address of said first sector if the current address has been erased;

(f) increasing the current address by one if the current address is not the last address and repeating steps (c)-(e);

(g) turning OFF said erase-on signal if the current address is the last address and proceeding to the second sector of said plurality of sectors;

repeating steps (a) through (g) for the remaining sectors of said plurality of sectors except for a last sector;

determining whether the last sector of said plurality of sectors has its erase-on signal turned OFF;

determining whether the erase-on signal for all sectors of said plurality of sectors are turned OFF if the last sector has its erase-on signal turned OFF;

(i) determining whether the current address of the last sector has been turned OFF if said erase-on signal is not turned OFF;

(j) storing current address in an address register if the current address is not erased;

(k) determining whether the current address is a last address of said last sector if the current address has been erased;

increasing the current address by one if the current address is not the last address and repeating steps (i) through (k);

turning OFF said erase-on signal if the current address is the last address;

applying an erase pulse to all bytes in all sectors simultaneously in which the erase-on signals have not been turned OFF if the current address of the last sector has not been erased or if the erase-on signal for all sectors have not been turned OFF and repeating steps (a) through (k); and

terminating the erasing operation when the erase-on signal has been turned OFF in all sectors of said plurality of sectors.

2. A unified erase method as claimed in claim 1, wherein the step of programming initially all bytes includes the step of setting all bytes to a state “

1”

.

3. A unified erase method as claimed in claim 2, wherein the step of determining whether the current address has been erased includes the step of checking if the current address is set to a state “

1”

.

4. A unified erase method as claimed in claim 3, wherein the step of applying the erase pulse includes the step of beginning an erase-verify operation at the current address stored for each sector.

5. A unified erase method as claimed in claim 4, wherein each of said sectors is arranged in rows and columns and wherein said corresponding register stores the row and column of the current address that has not been erased.

6. A unified erase method as claimed in claim 4, wherein each of said sectors is arranged in rows and columns and wherein said corresponding register stores only the row of the current address that has not been erased.

7. A unified erase method as claimed in claim 4, wherein each sector is arranged in rows and columns and said corresponding register stores every predetermined number of rows of the current address that has not been erased.

8. A unified erase method used in an array of flash EEPROM memory cells arranged in a plurality of sectors for performing either a single-sector, multiple-sector, or all-sector erasing operation with a reduced amount of total erase time, said erase method comprising the steps of:

selectively turning ON an erase-on signal in only certain ones of said plurality of sectors which are required to be erased;

programming initially all bytes in said certain ones of said plurality of sectors which are required to be erased;

setting current address in said certain ones of said plurality of sectors which are required to be erased to a first address;

determining whether each sector of said plurality of sectors has its corresponding erase-on signal turned OFF;

sequentially performing an erase-verify operation on said plurality of sectors from a first sector to a last sector beginning with the first address of said sector if its said corresponding erase-on signal is not turned OFF;

turning OFF said corresponding erase-on signal for each sector that has passed the erase-verify operation;

storing current address of each sector at a point where the erase-verify operation failed;

applying an erase pulse simultaneously to all sector that has not passed the erase-verify operation and repeating the erase-verify operation beginning at the current address stored; and

terminating the erasing operation when the erase-on signal has been turned OFF in all sectors of said plurality of sectors.

9. A unified erase method as claimed in claim 8, wherein said erase-verify operation includes the step of checking whether each address in the sector has been erased.

10. A unified erase method as claimed in claim 8, wherein each of said sectors is arranged in rows and columns and wherein said corresponding register stores the row and column of the current address that has not been erased.

11. A unified erase method as claimed in claim 8, wherein each of said sectors is arranged in rows and columns and wherein said corresponding register stores only the row of the current address that has not been erased.

12. A unified erase method as claimed in claim 8, wherein each sector is arranged in rows and columns and said corresponding register stores every predetermined number of rows of the current address that has not been erased.