Semiconductor memory device and regulator

• US 6,172,917 B1
• Filed: 05/11/1999
• Issued: 01/09/2001
• Est. Priority Date: 05/12/1998
• Status: Expired due to Term

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Kataoka, Tomonori, Fuchigami, Ikuo, Nishida, Yoichi, Kimura, Tomoo, Michiyama, Junji
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, THONG QUOC
• Application Number:
  US09/309,581
• Time in Patent Office: 609 Days
• Field of Search: 365/203, 365/189.05, 365/218, 365/185.22, 365/185.29, 365/185.25, 365/241, 365/189.11
• US Class Current: 365/189.05
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A semiconductor memory device having nonvolatile memory cells arranged in matrix comprises and bit lines connected to drains of the memory cells. Latches provided for the respective bit lines or in the ratio of one latch to a number of bit lines, as are; transfer gates for electrically separating the respective latches from the bit lines. The device also having bit line voltage detection circuits for detecting voltages of the respective bit lines and latch reset circuits for inverting data stored in the respective latches in accordance with the outputs from the bit line voltage detection circuits. Therefore, data stored in each latch can be rewritten even by a very small memory cell current, resulting in stable program verify.

Claims

1. A semiconductor memory device, comprising:

nonvolatile memory cells being arranged in a matrix;

bit lines being connected to drains of said memory cells;

latches, each of said latches being connected to a respective one of said bit lines or in a ratio of one latch to a number of said bit lines;

transfer gates being operable to electrically separate said latches from said bit lines;

bit line voltage detection circuits being operable to detect absolute voltages of said bit lines; and

latch reset circuits being operable to invert data stored in said latches in accordance with outputs from said bit line voltage detection circuits.

2. A semiconductor memory device claimed in claim 1, further comprising:

precharging means for precharging a bit line connected to a drain of a selected memory cell selected from said bit lines connected to the drains of said memory cells when performing program verify to decide whether programming of said memory cell has been properly performed;

applying means for applying a program verify voltage to a word line of the selected memory cell during the program verify; and

bit line voltage detecting means for detecting a bit line voltage which is determined by a cell current of the selected memory cell in the program verify, wherein each of said latch reset circuits is operable to invert the data stored in the respective one of said latches based on output from said bit line voltage detecting means.

3. A semiconductor memory device, comprising:

nonvolatile memory cells being arranged in a matrix;

bit lines being connected to drains of said memory cells;

latches, each of said latches being connected to a respective one of said bit lines or in a ratio of one latch to a number of said bit lines;

transfer gates being operable to electrically separate said latches from said bit lines;

level shift circuits being operable to convert output levels of said latches to a program voltage and a verify drain voltage and further operable to output the program voltage and the verify drain voltage to said bit lines via said transfer gates;

bit line voltage detection circuits being operable to detect absolute voltages of said bit lines; and

latch reset circuits being operable to invert data stored in said latches in accordance with outputs from said bit line voltage detection circuits.

4. A semiconductor memory device, comprising:

nonvolatile memory cells being arranged in a matrix;

bit lines being connected to drains of said memory cells;

latches being operable to store data, each of said latches being connected to a respective one of said bit lines or in a ratio of one latch to a number of said bit lines;

precharging means for precharging a bit line connected to a drain of a selected memory cell selected from said bit lines connected to the drains of said memory cells when performing program verify to decide whether programming of the selected memory cell has been properly performed, wherein the data stored in said latches are inverted according to voltages of said bit lines;

applying means for applying a program verify voltage to a word line of the selected memory cell in the program verify; and

applying means for applying a negative voltage to word lines other than the word line of the selected memory cell.

5. A semiconductor device, comprising:

nonvolatile memory cells being arranged in a matrix;

bit lines being connected to drains of said memory cells;

latches, each of said latches being connected to a respective one of said bit lines or in a ratio of one latch to a number of said bit lines;

transfer gates being operable to electrically separate said latches from said bit lines;

bit line voltage detection circuits being operable to detect absolute voltages of said bit lines;

latch reset circuits being operable to invert data stored in said latches in accordance with outputs from said bit line voltage detection circuits; and

verify pulse generation circuits being connected to said bit line voltage detection circuits and being operable to generate arbitrary pulse widths.

6. A semiconductor device claimed in claim 5, further comprising:

precharging means for precharging a bit line connected to a drain of a selected memory cell selected from said bit lines connected to the drains of said memory cells when performing program verify to decide whether programming of the selected memory cell has been properly performed;

applying means for applying a program verify voltage to a word line of the selected memory cell during the program verify;

setting means for setting word lines other than the word line of the selected memory cell to zero volts or a negative voltage;

executing means for executing program verify during a period of a verify pulse generated from said pulse generation circuits;

setting means for setting a low threshold voltage of the selected memory cell by setting a short pulse width of a programming pulse; and

setting means for setting a high threshold voltage of the selected memory cell by setting a long pulse width of a programming pulse.

7. A semiconductor memory device, comprising:

nonvolatile memory cells being arranged in a matrix;

a regulator comprising;

generating means for generating a reference voltage,

dividing means for dividing an output voltage into a first integer number (n−

1) of stages using a second integer number (n) of resistive elements connected in series, wherein the second number is one integer greater than the first number,

short-circuiting means for short-circuiting one of said resistive elements with an output section to create a divided voltage, wherein said one of said resistive elements is an integer number element (m) that is not larger than two integers less than the second integer number (n−

2);

setting means for setting a resistance of the output section at an arbitrary value with said short-circuiting means,

comparing means for comparing the divided voltage with the reference voltage, and

output means for outputting a third number of stable voltages which are multiples of the reference voltage, wherein the third number is equal to the first number; and

output means for outputting a first voltage to be applied to said nonvolatile memory cells when reading data, a second voltage to be applied to said nonvolatile memory cells programming data, and a third voltage to be applied to said nonvolatile memory cells when erasing data, by using said regulator.

8. A semiconductor memory device claimed in claim 7, further comprising:

bit lines being connected to drains of said nonvolatile memory cells;

latches, each of said latches being connected to a respective one of said bit lines or in a ratio of one latch to a number of said bit lines;

transfer gates being operable to electrically separate said latches from said bit lines;

bit line voltage detection circuits being operable to detect voltages of said bit lines;

latch reset circuits being operable to invert data stored in said latches in accordance with outputs from said bit line voltage detection circuits;

a booster circuit being operable to internally generate a high voltage to be applied to said regulator from a power supply voltage applied to said semiconductor memory device;

a decoder having a power supply and being operable to output a plurality of voltages, wherein an output of said regulator is connected to the power supply of said decoder.

9. A semiconductor memory device claimed in claim 7, further comprising:

bit lines being connected to drains of said nonvolatile memory cells;

latches, each of said latches being connected to a respective one of said bit lines or in a ratio of one latch to a number of said bit lines, wherein an output of said regulator is connected to a power supply for each of said latches and a plurality of voltages are output from each of said latches to the respective one of said bit lines;

transfer gates being operable to electrically separate said latches from said bit lines;

bit line voltage detection circuits being operable to detect voltages of said bit lines;

latch reset circuits being operable to invert data stored in said latches in accordance with outputs from said bit line voltage detection circuits; and

a booster circuit being operable to internally generate a high voltage to be applied to said regulator from a power supply voltage applied to said semiconductor memory device.

10. A semiconductor memory device claimed in claim 7, further comprising:

bit lines being connected to drains of said nonvolatile memory cells;

latches, each one of said latches being connected to a respective one of said bit lines or in a ratio of one latch to a number of said bit lines;

transfer gates being operable to electrically separate said latches from said bit lines;

bit line voltage detection circuits being operable to detect voltages of said bit lines;

latch reset circuits being operable to invert data stored in said latches in accordance with outputs from said bit line voltage detection circuits;

level shift circuits being operable to convert output levels of said latches to a program voltage and a verify drain voltage, wherein an output of said regulator is connected to a power supply for each of said level shift circuits, and plural kinds of voltages are supplied from said latches through said level shift circuits to said bit lines; and

a booster circuit being operable to internally generate a high voltage to be applied to said regulator from a power supply voltage applied to said semiconductor memory device.

11. A semiconductor device, comprising:

nonvolatile memory cells being arranged in a matrix;

bit lines being connected to drains of said memory cells;

flip-flops, each said flip-flop being provided for a respective one of said bit lines or in a ratio of one flip-flop to a number of said bit lines;

shift registers, each said shift register being constructed by connecting two adjacent flip-flops such that a data input terminal of one of the flip-flops is connected to a data output terminal of another of the flip-flops;

transfer gates being operable to electrically separate said flip-flops from said bit lines;

bit line voltage detection circuits being operable to detect absolute voltages of said bit lines;

flip-flop reset circuits being operable to invert data stored in said flip-flops in accordance with outputs from said bit line voltage detection circuits; and

setting means for setting data to be programmed by serially inputting data to said shift registers.

12. A semiconductor device, comprising:

nonvolatile memory cells being arranged in a matrix;

bit lines being connected to drains of said memory cells;

flip-flops, each of said flop-flops being provided for a respective one of said bit lines or in a ratio of one flip-flop to a number of said bit lines;

shift registers, each of said shift registers being constructed as connecting two adjacent flip-flops such that a data input terminal of one of the flip-flops is connected to a data output terminal of another of the flip-flops;

transfer gates being operable to electrically separate said flip-flops from said bit lines;

level shift circuits being operable to convert output levels of said flip-flops to a program voltage and a verify drain voltage and further operable to output the program voltage and the verify drain voltage to said bit lines via said transfer gates;

bit line voltage detection circuits being operable to detect absolute voltages of said bit lines;

flip-flop reset circuits being operable to invert data stored in said flip-flops in accordance with outputs from said bit line voltage detection circuits; and

setting means for setting data to be programmed by serially inputting data to said shift registers.

13. A semiconductor memory device, comprising:

nonvolatile memory cells being arranged in a matrix;

word lines being connected to control gates of said nonvolatile memory cells;

bit lines being connected to drains of said nonvolatile memory cells;

source lines being connected to sources of said nonvolatile memory cells;

latches, each of said latches being connected to a respective one of said bit lines or in a ratio of one latch to a number of said bit lines; and

a control circuit operable to perform an erasing operation on said nonvolatile memory cells in advance of performing a programming operation on said nonvolatile memory cells and further operable to perform a preprogramming for setting a memory cell in an erased state to a programed state prior to the erasing operation performed in advance of the programming operation.

14. A semiconductor memory device, comprising:

nonvolatile memory cells being arranged in a matrix;

performing means for performing a program verify of a memory cell of said nonvolatile memory cells after programming has been performed to decide if the programming has been properly performed;

performing means for performing reprogramming to the memory cell when the result of the program verify is failure;

reducing means for arbitrarily reducing a number of times the program verify is performed as a number of times of programming increases; and

performing means for performing programming continuously when a number of times programming is performed decreases.

15. A semiconductor memory device claimed in claim 14, wherein when said semiconductor memory device is performing the programming and the program verify to the memory cell in a sequence to execute the program verify after the programming, assuming that a predetermined pulse width is Tpreg, the number of times of program verify is n, and an elapse time Tpv from the start of the programming, the elapse time corresponding to a timing at which the program verify is to be performed, said semiconductor memory device is operable to perform the program verify with a timing that satisfies the following relationship:

16. A semiconductor memory device claimed in claim 14, wherein when said semiconductor memory device is performing the programming and the program verify to the memory cell in a sequence to execute the program verify after the programming, assuming that a number of times of program verify is n, a verify point Ppv which indicates the number of time of programming after which the program verify is to be performed corresponding to a timing at which the program verify is to be performed, said semiconductor memory device is operable to perform the program verify with a timing that satisfies the following relationship:

17. A semiconductor memory device, comprising:

nonvolatile memory cells being arranged in a matrix;

bit lines being connected to drains of said nonvolatile memory cells;

latches, each of said latches being connected to a respective one of said bit lines or in a ratio of one latch to a number of said bit lines;

transfer gates being operable to electrically separate said latches from said bit lines;

selecting means for selecting a bit line for programming in accordance data stored in said latches connected to said bit lines;

performing means for performing program verify to decide whether programming has been properly performed;

performing means for performing the program verify after the programming has been performed; and

performing means for performing additional programming by adding a programming pulse when a result of the program verify indicates that the programming has been properly performed.