Semiconductor memory device allowing high-speed operation of internal data buses

• US 6,172,918 B1
• Filed: 06/03/1999
• Issued: 01/09/2001
• Est. Priority Date: 12/08/1998
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Hidaka, Hideto
• Primary Examiner(s): Tran, Andrew Q.
• Application Number:
  US09/327,155
• Time in Patent Office: 586 Days
• Field of Search: 365/189.11, 365/230.03, 365/202, 365/190, 365/189.05
• US Class Current: 365/189.11
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Abstract

A current mirror-type load circuit is provided for a global data line pair. A read gate amplifier used as a block select gate for each of the local data line pairs. A read gate amplifier includes a MOS transistor having its gate connected to a corresponding local data line. A data write driver writes the logic-inverted data of the write data upon equalization after the data write operation. A high-speed access becomes possible by reducing the time required for reading of data and by reducing the write recovery time.

Claims

1. A semiconductor memory device, comprising:

a plurality of memory blocks each having a plurality of memory cells arranged in a matrix of rows and columns, and arranged in alignment at least in a column-direction;

a plurality of local data line pairs provided corresponding to said memory blocks, each of said plurality of local data line pairs being coupled to a selected memory cell in a corresponding memory block;

a global data line pair provided in common to the memory blocks arranged in alignment in the column-direction;

a plurality of read gate amplifiers each provided between each of said plurality of local data line pairs and said global data line pair, for transmitting, when selected, a signal of a corresponding local data line pair to said global data line pair, with said corresponding local data line pair and said global data line pair being electrically isolated; and

a current supply load circuit coupled to said global data line pair for supplying a current of a same magnitude to each data line of said global data line pair.

2. The semiconductor memory device according to claim 1, wherein each of the read gate amplifiers includes a pair of insulated gate field effect transistors each having a gate connected to a local data line of a corresponding local data line pair.

3. The semiconductor memory device according to claim 1, wherein said current supply load circuit includes a current mirror circuit.

4. The semiconductor memory device according to claim 1, further comprising a write gate provided for each of the local data line pairs for electrically connecting said global data line pair to a corresponding local data line pair in response to a block select signal in a data write mode.

5. The semiconductor memory device according to claim 2, wherein each of the read gate amplifiers further includes a select transistor pair connected in series with the field effect transistor pair and rendered conductive in response to a block select signal in a read operation, and said field effect transistor pair and said select transistor pair are connected in series between said global data line pair and a reference voltage node.

6. The semiconductor memory device according to claim 5, further comprising an equalizing circuit coupled to said global data line pair for equalizing voltages of said global data line pair in response to an equalizing instruction signal and a write circuit for generating an internal write data according to an externally applied write data and transmitting the internal write data to said global data line pair, wherein said write circuit generates a logic-inverted data of said internal write data in response to activation of said equalizing instruction signal and transmitting the logic-inverted data to said global data line pair.

7. The semiconductor memory device according to claim 6, wherein said write circuit includes

a latch circuit for latching a first internal write data produced according to the externally applied write data,

a scramble circuit coupled to said latch circuit, for producing complementary data signals in accordance with the first internal write data received from the latch circuit, said scramble circuit including a gating circuit for exchanging paths of transferring the complementary data signals in response to activation of the equalizing instruction signal, and

a buffer driver for driving the global data line pair in accordance with the complementary data signals to transmit a second internal write data to the global data line pair when one of said equalizing instruction signal and a data write enabling signal is active.

8. The semiconductor memory device according to claim 6, wherein said write circuit includes

a latch circuit for latching a first internal write data produced according to the externally applied write data,

a scramble circuit coupled to said latch circuit, for producing complementary data signals in accordance with the first internal write data received from the latch circuit, said scramble circuit including a gate circuit for inverting the complementary data signals in response to activation of said equalizing instruction signal, and

a driver for driving the global data line pair in accordance with the complementary data signals received from the scramble circuit to transmit a second internal write data onto the global data line pair.

9. The semiconductor memory device according to claim 6, wherein said write circuit includes

a latch circuit for latching a first internal write data produced according to the externally applied write data, and

a scramble/dive circuit coupled to said latch circuit, for producing complementary data signals according to the first internal write data to drive the global data line pair in accordance with the complementary data signals and for transmitting a second internal write data onto the global data line pair, said scramble/drive circuit including a first drive circuit activated in response to a data write enabling signal being active for driving the global data line pair in accordance with the complementary data signals, and a second drive circuit activated in response to activation of the equalizing instruction signal, for driving the global data line pair in a manner opposite to driving of the first drive circuit.

10. A semiconductor memory device, comprising:

a plurality of memory cells;

an internal data line pair for transmitting write data to a selected memory cell of said plurality of memory cells;

an equalizing circuit coupled to said internal data line pair for equalizing voltages of said internal data line pair in response to an equalizing instruction signal; and

a write circuit for generating an internal write data according to an externally applied write data and transmitting the internal write data to said internal data line pair, said write circuit generating a logic-inverted data of said internal write data in response to activation of said equalizing instruction signal and transmitting the logic-inverted data to said internal data line pair.

11. The semiconductor memory device according to claim 10, wherein said internal data line pair further transmits internal read data read out from said selected memory cell.

12. The semiconductor memory device according to claim 10, wherein said write circuit includes a latch circuit for latching said internal write data, an internal data generating circuit for receiving latch data from said latch circuit in deactivation of said equalizing instruction signal and outputting the latch data, and for logic-inverting the latch data received from said latch circuit in response to activation of said equalizing instruction signal and outputting logic-inverted latch data.

13. The semiconductor memory device according to claim 12, further comprising a drive circuit for driving said internal data line pair according to the data output from said internal data generating circuit.

14. The semiconductor memory device according to claim 10, further comprising a load circuit coupled to said internal data line pair.

15. A semiconductor memory device, comprising:

a plurality of array blocks each including a plurality of memory cells arranged in a matrix of rows and columns and a plurality of bit line pairs arranged corresponding to the columns and connecting memory cells of corresponding columns;

a plurality of local data line pairs arranged extending in a row-direction and corresponding to said plurality of array blocks;

a plurality of column select gates disposed corresponding to said plurality of bit line pairs in each of said plurality of array blocks, for electrically connecting a bit line pair corresponding to a selected column to a corresponding local data line pair in response to a column select signal;

a global data line pair extending in a column-direction and arranged in common to array blocks, of said plurality of array blocks, disposed in alignment in the column-direction;

a plurality of read gates each provided between each of said local data line pairs and said global data line pair, each of said plurality of read gates including a select gate pair made conductive in response to a block select signal activated according to an address signal in a data read mode, and a differential gate pair including an insulated gate field effect transistor receiving a signal on a corresponding local data line pair at a gate thereof, said differential gate pair and said select gate pair being connected in series between said global data line pair and a reference voltage node; and

a current mirror-type load circuit coupled to said global data line pair, for supplying, when activated, current to said global data line pair.

16. A semiconductor memory device comprising:

a plurality of memory blocks each having a plurality of memory cells arranged in a matrix of rows and columns;

a plurality of local data line pairs provided corresponding to said plurality of memory blocks, each for communicating data with a selected memory cell in a corresponding memory block;

a global data line pair provided in common to the memory blocks;

a plurality of read gate amplifiers each provided between each of said plurality of local data line pairs and said global data line pair, for transmitting, when selected, a signal of a corresponding local data line pair to said global data line pair; and

a current supply load circuit coupled to said global data line pair for supplying a current to each data line of said global data line pair.

17. The semiconductor memory device according to claim 16, wherein each of said plurality of read gate amplifiers includes an input transistor pair including insulated gate field effect transistors having gates respectively connected to local data lines of a corresponding local data line pair.

18. The semiconductor memory device according to claim 17, wherein each of said plurality of read gate amplifiers further includes a select transistor pair connected in series with said input transistor pair and turned on in response to a block select signal in a read operation, and said input transistor pair and said select transistor pair are connected in series between said global data line pair and a predetermined voltage node.

19. The semiconductor memory device according to claim 18, wherein said select transistor pair is connected to said global data line pair, and said input transistor pair is connected between said select transistor pair and said predetermined voltage node.

20. The semiconductor device according to claim 16, wherein said current supply load circuit includes a current mirror circuit.

21. The semiconductor memory device according to claim 16, further comprising a plurality of write gates provided corresponding to said plurality of local data line pairs, each for electrically connecting said global data line pair to a corresponding local data line pair in response to a block select signal write operation.

22. The semiconductor memory device according to claim 21, further comprising:

a equalizing circuit coupled to said global data line pair for equalizing voltages of said global data line pair in response to an equalizing instruction signal; and

a write circuit for generating an internal write data according to an externally applied write data and transmitting the internal write data to said global data line pair, and for generating a logic-inverted data of said internal write data in response to activation of said equalizing instruction signal and transmitting the logic-inverted data to said global data line pair.

23. The semiconductor memory device according to claim 22, wherein said write circuit includes:

a latch circuit for latching a first internal write data produced according to the externally applied write data,

a scramble circuit coupled to said latch circuit, for producing complementary data signals in accordance with the first internal write data received from said latch circuit, said scramble circuit including a gate circuit for exchanging paths of transferring the complementary data signals in response to activation of the equalizing instruction signal, and

a buffer driver for driving said global data line pair in accordance with the complementary data signals to transmit a second internal write data to said global data line pair when one of said equalizing instruction signal and a data write enabling signal is active.

24. The semiconductor memory device according to claim 22, wherein said write circuit includes:

a latch circuit for latching a first internal write data produced according to the externally applied write data,

a scramble circuit coupled to said latch circuit, for producing complementary data signals in accordance with the first internal write data received from said latch circuit, said scramble circuit including a gate circuit for inverting the complementary data signals in response to activation of the equalizing instruction signal, and

a driver for driving said global data line pair in accordance with the complementary data signals received from said scramble circuit to transmit a second internal write data onto said global data line pair.

25. The semiconductor memory device according to claim 22, wherein said write circuit includes:

a latch circuit for latching a first internal write data produced according to the externally applied write data, and

a scramble/drive circuit coupled to said latch circuit, for producing complementary data signals according to the first internal write data to drive said global data line pair in accordance with the complementary data signal, and for transmitting a second internal write data onto said global data line pair, said scramble/drive circuit including a first drive circuit activated in response to a data write enabling signal being active for driving said global data line pair in accordance with the complementary data signals, and a second drive circuit activated in response to activation of the equalizing instruction signal, for driving said global data line pair in a manner opposite to driving of the first drive circuit.

26. The semiconductor memory device according to claim 16, wherein the read gate amplifier is selected in said plurality of read gate amplifiers in response to block select signals.

27. The semiconductor memory device according to claim 16, further comprising a switch coupled between said current supply load circuit and a power supply, for electrically separating said current supply load circuit from the power supply in a write operation.