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Control loop for data signal baseline correction

  • US 6,173,019 B1
  • Filed: 05/12/1998
  • Issued: 01/09/2001
  • Est. Priority Date: 12/10/1997
  • Status: Expired due to Term
First Claim
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1. An apparatus including a control loop for controlling a baseline correction of a data signal, comprising:

  • a baseline correction circuit configured to receive and combine a baseline correction signal and an input data signal having a data signal baseline associated therewith and in accordance therewith provide a corrected data signal with a substantially fixed baseline;

    a data signal peak detection circuit, coupled to said baseline correction circuit, configured to receive and detect said corrected data signal and in accordance therewith provide a plurality of peak parameter signals which indicates whether said corrected data signal has transcended a plurality of predetermined signal levels including predetermined minimum and maximum signal levels which are respectively below and above a mean value of said corrected data signal;

    a data signal mean detection circuit, coupled to said baseline correction circuit, configured to receive and detect said corrected data signal and in accordance therewith provide a first baseline parameter signal which indicates whether said corrected data signal is within a predetermined range of values intermediate to said predetermined minimum and maximum signal levels, and provide a second baseline parameter signal which indicates a polarity of said corrected data signal relative to said mean value of said corrected data signal;

    a signal processing circuit, coupled to said data signal peak detection circuit, configured to receive and process said plurality of peak parameter signals and in accordance therewith provide a third baseline parameter signal which indicates a difference between said corrected data signal and said mean value of said corrected data signal; and

    a baseline control circuit, coupled to said data signal mean detection circuit, said signal processing circuit and said baseline correction circuit, configured to receive and process said first, second and third baseline parameter signals and in accordance therewith provide said baseline correction signal.

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