External apparatus for combining partially defected synchronous dynamic random access memories
First Claim
1. An apparatus for combining partially defected synchronous dynamic random access memory chips as a functional SDRAM chip, said apparatus comprising:
- a plurality of partially defected synchronous dynamic random access memory chips;
a reference signal means for generating a reference signal;
a workable block selecting circuit being responsive to said reference signal for selecting workable blocks of said plurality of partially defected synchronous dynamic random access memory chips; and
a chip selecting circuit being responsive to a chip selecting signal and said reference signal for selecting a chip from said plurality of partially defected synchronous dynamic random access memory chips to access data as a defect-free chip by said selected workable blocks.
2 Assignments
0 Petitions
Accused Products
Abstract
The present invention discloses an apparatus for combining partially defected synchronous dynamic random access memories. By selecting each memory chip with corresponding workable blocks, the partially defected SDRAMs can be combined as a workable device which can be programmed and operated in the same way as a defect-free chip. The apparatus for combining partially defected synchronous dynamic random access memory chips of the present invention includes a workable block selecting circuit and a chip selecting circuit. The workable block selecting circuit is responsive to a reference signal for selecting workable blocks of the synchronous dynamic random access memories. The chip selecting circuit is responsive to a chip selecting signal and the reference signal for selecting a chip from the synchronous dynamic random access memory chips.
-
Citations
19 Claims
-
1. An apparatus for combining partially defected synchronous dynamic random access memory chips as a functional SDRAM chip, said apparatus comprising:
-
a plurality of partially defected synchronous dynamic random access memory chips;
a reference signal means for generating a reference signal;
a workable block selecting circuit being responsive to said reference signal for selecting workable blocks of said plurality of partially defected synchronous dynamic random access memory chips; and
a chip selecting circuit being responsive to a chip selecting signal and said reference signal for selecting a chip from said plurality of partially defected synchronous dynamic random access memory chips to access data as a defect-free chip by said selected workable blocks. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
-
-
15. A method for combining a plurality of partially defected synchronous dynamic random access memory chips as a functional SDRAM chip, comprising the steps of:
-
providing a plurality of partially defected synchronous dynamic random access memory chips;
inputting a reference signal to a workable block selecting circuit for generating a workable block selecting signal;
selecting workable blocks of said plurality of partially defected synchronous dynamic random access memory chips in response to said workable block selecting signal;
inputting a chip selecting signal and said reference signal to said chip selecting circuit for generating a controlling signal;
selecting a chip from said plurality of partially defected synchronous dynamic random access memory chips in response to said controlling signal; and
combining said workable block selecting signal and said controlling signal to activate said selected workable block of said selected chip for data access. - View Dependent Claims (16, 17, 18, 19)
-
Specification