Computer system having dual bus architecture with audio/video/CD drive controller/coprocessor having integral bus arbitrator

• US 6,173,358 B1
• Filed: 02/13/1998
• Issued: 01/09/2001
• Est. Priority Date: 12/16/1993
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Combs, James Lee
• Primary Examiner(s): Thai, Tuan V.
• Application Number:
  US09/023,904
• Time in Patent Office: 1,061 Days
• Field of Search: 711/3, 711/100, 711/115, 711/151, 711/154, 711/158, 711/159
• US Class Current: 711/100
• CPC Class Codes: A63F 2300/201 Playing authorisation given at platform level
• CPC Class Codes: A63F 2300/206 Game information storage, e.g. cartridges, CD ROM's, DVD's, smart cards
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 21/10 Protecting distributed programs or content, e.g. vending or licensing of copyrighted material protection in video systems or pay television H04N7/16 ; Digital rights management [DRM]
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 2207/7219 Countermeasures against side channel or fault attacks
• CPC Class Codes: G06F 2221/2109 Game systems
• CPC Class Codes: G06F 2221/2121 Chip on media, e.g. a disk or tape with a chip embedded in its case

Abstract

A computer system for high-performance video and audio manipulations comprising a locked memory cartridge and an audio/video/compact disk (CD) drive controller/coprocessor. The computer system has a central processing unit (CPU) with at least one bus associated therewith, with the bus having at least one bus line. The cartridge comprises a readable memory, a memory control circuit, a lock control circuit, and a connector all in circuit communication with each other. The connector allows the memory, the memory control circuit, and the lock control circuit to be pluggably connected in circuit communication with the CPU. The memory control circuit scrambles some of the bus lines, thereby scrambling the data in the memory on reset, and unscrambles the bus lines responsive to inputs from the lock control circuit. The lock control circuit monitors the bus, waiting for a proper combination of bus values to be asserted onto the bus, at which time the lock control circuit causes the memory control circuit to unscramble the bus lines. The audio/video/CD drive controller/coprocessor comprises a CPU interface, a CPU cache, a memory controller, a memory bus arbitrator, a DRAM refresher, a video controller, a CD drive controller, a digital signal processor (DSP) sound coprocessor, and a “blitter” graphics coprocessor in an integrated package.

Claims

1. A computer system comprising:

(a) a central processing unit (CPU) in circuit communication with an audio/video/CD drive controller/co-processor (A/V/CD controller/co-processor) via a first system bus;

(b) a system memory in circuit communication with said A/V/CD controller/co-processor via a second system bus; and

(c) an additional memory element in circuit communication with said CPU via said first system bus;

(d) said A/V/CD controller/co-processor further including an arbitrator for arbitrating control over said second system bus, an integral memory interface, an integral graphics coprocessor, an integral digital signal processor, an integral compact disk controller, and an integral video controller all in circuit communication with said CPU and said system memory and each configured such that any one of said CPU, said graphics co-processor, said digital signal processor, said compact disk controller, and said video controller may become bus master of said second system bus; and

said CPU may directly access said additional memory element while said A/V/CD controller/coprocessor performs functions with said system memory through said second system bus;

(e) an interrupt controller for interfacing interrupts to said CPU and said arbitrator responsive to said interrupt controller such that said CPU does not have the highest priority for control over said second system bus until an interrupt occurs and is detected by said interrupt controller.

2. A computer system according to claim 1 wherein said integral memory interface, said integral graphics coprocessor, said integral digital signal processor, said integral compact disk controller, and said integral video controller are electrically connected within said A/V/CD controller/coprocessor via an internal bus such that said second system bus makes one bus connection with said A/V/CD controller/coprocessor at said internal bus.

3. A computer system according to claim 1 wherein said integral memory interface, said integral graphics coprocessor, said integral digital signal processor, said integral compact disk controller, and said integral video controller are electrically connected within said A/V/CD controller/coprocessor via an internal bus such that said second system bus makes one bus connection with said A/V/CD controller/coprocessor at said internal bus.

4. A computer system according to claim 3 wherein said CPU has the lowest priority for accessing said second system bus as compared to the priority levels for said integral memory interface, said integral graphics coprocessor, said integral digital signal processor, said integral compact disk controller, and said integral video controller, until an interrupt occurs, at which time said CPU has the highest priority for accessing said second system bus.

5. The computer system of claim 1 wherein said additional memory element is a cache.

6. The computer system of claim 1 wherein said A/V/CD controller/coprocessor further comprises said additional memory element, and said additional memory element is an integral cache.

7. The computer system of claim 1 wherein said additional memory element is a cartridge ROM.