Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor

• US 6,173,389 B1
• Filed: 12/04/1998
• Issued: 01/09/2001
• Est. Priority Date: 12/04/1997
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Billions Of Operations Per Second, Inc. (Intel Corporation)
• Inventors: Pechanek, Gerald G., Barry, Edwin F., Revilla, Juan Guillermo
• Primary Examiner(s): Treat, William M.
• Application Number:
  US09/205,588
• Time in Patent Office: 767 Days
• Field of Search: 712/24, 712/210, 712/10, 712/20, 712/21, 712/22, 712/200, 712/203, 712/208, 712/212, 712/215, 712/226
• US Class Current: 712/24
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3853 of compound instructions

Abstract

A pipelined data processing unit includes an instruction sequencer and n functional units capable of executing n operations in parallel. The instruction sequencer includes a random access memory for storing very-long-instruction-words (VLIWs) used in operations involving the execution of two or more functional units in parallel. Each VLIW comprises a plurality of short-instruction-words (SIWs) where each SIW corresponds to a unique type of instruction associated with a unique functional unit. VLIWs are composed in the VLIW memory by loading and concatenating SIWs in each address, or entry. VLIWs are executed via the execute-VLIW (XV) instruction. The iVLIWs can be compressed at a VLIW memory address by use of a mask field contained within the XV1 instruction which specifics which functional units are enabled, or disabled, during the execution of the VLIW. The mask can be changed each time the XV1 instruction is executed, effectively modifying the VLIW every time it is executed. The VLIW memory (VIM) can be further partitioned into separate memories each associated with a function decode-and-execute unit. With a second execute VLIW instruction XV2, each functional unit'"'"'s VIM can be independently addressed thereby removing duplicate SIWs within the functional unit'"'"'s VIM. This provides a further optimization of the VLIW storage thereby allowing the use of smaller VLIW memories in cost sensitive applications.

Claims

1. An indirect very long instruction word (VLIW) processor comprising

a plurality of execution units capable of performing a plurality of distinct operations in parallel;

a VLIW memory (VIM) for storing VLIWs;

an execute VLIW (XNV instruction containing an offset value; and

an addressing mechanism for providing access to each memory entry in VIM, said memory entries each containing at least one instruction slot associated with a unique execution unit, said addressing mechanism comprising a base address register and adder employed in connection with each processing element operable to generate a VIM address by performing a base plus offset calculation utilizing the offset value from the XV instruction for each VLIW access.

2. The indirect VLIW processor of claim 1 further comprising at least one state bit associated with each instruction slot, said state bit designating whether an instruction is available-for-execution or not-available-for-execution.

3. The indirect VLIW processor of claim 1 wherein said instruction contains a field to specify the offset address, said XV instruction further comprising at least one mask enable bit.

4. The indirect VLIW processor of claim 1 wherein said plurality of execution units comprise a store unit, a load unit, an arithmetic-logic unit, a multiply-accumulate unit and a data select unit.

5. The indirect VLIW processor of claim 1 wherein said memory units each contain a store instruction slot, a load instruction slot, an arithmetic-logic instruction slot, a multiply-accumulate instruction slot, and a data-select unit slot.

6. The indirect VLIW processor of claim 1 wherein said addressing mechanism comprises a base VIM address register for storing a base VIM address and an adder for adding the base VIM address and an offset (VIMOFF) to produce a VIM address.

7. The indirect VLIW processor of claim 3 wherein said instruction contains at least one mask enable bit per instruction slot and further comprising at least one storage latch for storing each mask enable bit.

8. The indirect VLIW processor of claim 7 further comprising at least one state bit associated with each instruction slot, said state bit designating whether an instruction is available-for-execution or not-available-for-execution, and an execution unit decoder which determines from the stored mask enable bit for the at least one storage latch and said state bit for its associated instruction slot whether an instruction is to execute or not.

10. The indirect VLIW processor of claim 1 further comprising at least one state bit associated with each VIM section, said state bit designating whether an instruction is available-for-execution or not-available-for-execution.

11. The indirect VLIW processor of claim 1 further comprising an instruction to execute VLIWs stored in VIM, said instruction containing a plurality of offset fields to specify a VIM address with one offset field per execution unit VIM.

12. The indirect VLIW processor of claim 11 wherein the plurality of execution units comprise a store unit, a load unit, an arithmetic-logic unit, a multiply-accumulate unit and a data-select unit.

9. An indirect very long instruction word (VLIW) processor comprising

a plurality of execution units capable of performing a plurality of distinct operations in parallel;

a VLIW memory (VIM) for storing VLIWs, said VIM being divided into separate VIM sections each of which is associated with one of said plurality of execution units, said VIM sections storing instructions in each of the memory entry slots;

an execute VLIW (XV) instruction containing an offset value; and

an addressing mechanism for each of said VIM sections providing access to each memory entry, in it associated VIM section independently, said addressing mechanism comprising a base address register and adder employed in connection with each processing element operable to generate a VIM address by performing a base plus offset calculation utilizing the offset value from the XV instruction for each VLIW access.

13. The indirect VLIW processor of claim 9 further comprising multiple VIM sections and wherein the offset (VimOffs) is an immediate field in the XV instruction and each VIM section has a separate addressing mechanism.

14. The indirect VLIW processor of claim 9 wherein said addressing mechanism comprises a base VIM address register for storing a base VIM address, an adder for adding the base VIM address for each of multiple VIM sections and the offset contained in the XV instruction is utilized by multiple addressing mechanisms to produce an address, and an incrementing mechanism is further utilized for loading instructions into the VIM in multiple VIM addresses.

15. A single instruction multiple data stream (SIMD) processor with a sequence processor (SP) and a plurality of processing elements (PEs), the SP and each PE comprising:

a plurality of execution units capable of performing a plurality of distinct operations in parallel;

a very long, instruction word (VLIW) memory (VIM) for storing VLIWs;

an execute VLIW (XV) instruction containing an offset value; and

an addressing mechanism for said VIM providing access to each memory entry in VIM, said memory entries each containing at least one instruction slot associated with a unique execution unit and at least one state bit associated with each instruction slot, designating whether an instruction is available-for-execution or not-available-for-execution, said addressing mechanism comprising a base address register and adder employed in connection with each processing clement operable to generate a VIM address by performing a base plus offset calculation utilizing the offset value from the XV instruction for each VLIW access.

16. The SIMD processor of claim 15 further comprising:

an instruction to execute VLIWs stored in VIM, said instruction containing a field to specify a VIM address, said instruction containing at least one mask bit to control the enabling or disabling of an execution unit at VLIW-instruction-execution-time.

17. The SIMD processor of claim 15 in which a plurality of different VLIW operations are packed into a single VLIW memory entry so that a plurality of programs can share a single VLIW memory entry.

18. A single instruction multiple data stream (SIMD) processor with a sequence processor (SP) and a plurality of processing elements (PEs), the SP and each PE comprising:

a plurality of execution units capable of performing a plurality of distinct operations in parallel;

a very long instruction word (VLIW) memory (VIM) for storing VLIWs, said VIM being divided into separate VIM sections each of which is associated with one of said plurality of execution units, said VIM sections storing instructions in each of the memory entry slots;

an execute VLIW (XV) instruction containing an offset value; and

an addressing mechanism for each of said VIM sections providing access to each memory entry, in it associated VIM section independently, said addressing mechanism comprising a base address register and adder employed in connection with each processing element operable to generate a VIM address by performing a base plus offset calculation utilizing the offset value from the XV instruction for each VLIW access.

19. The SMID processor of claim 18 further comprising at least one state bit associated with each VIM section, said state bit designating whether an instruction is available-for-execution or not-available-for-execution.

20. The SMID processor of claim 18 further comprising an instruction to execute VLIWs stored in VIM, said instruction containing a plurality of offset fields to specify a VIM address with one offset field per execution unit VIM.

21. The SMID processor of claim 18 wherein the plurality of execution units comprise a store unit, a load unit, an arithmetic-logic unit, a multiply-accumulate unit and a data-select unit.

22. The SMID processor of claim 18 wherein each PE and the SP include an addressing mechanism comprising a base VIM address register for storing a base VIM address and an adder for adding the base VIM address and the offset from the XV instruction to produce a VIM address.