Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor
First Claim
1. An indirect very long instruction word (VLIW) processor comprisinga plurality of execution units capable of performing a plurality of distinct operations in parallel;
- a VLIW memory (VIM) for storing VLIWs;
an execute VLIW (XNV instruction containing an offset value; and
an addressing mechanism for providing access to each memory entry in VIM, said memory entries each containing at least one instruction slot associated with a unique execution unit, said addressing mechanism comprising a base address register and adder employed in connection with each processing element operable to generate a VIM address by performing a base plus offset calculation utilizing the offset value from the XV instruction for each VLIW access.
5 Assignments
0 Petitions
Accused Products
Abstract
A pipelined data processing unit includes an instruction sequencer and n functional units capable of executing n operations in parallel. The instruction sequencer includes a random access memory for storing very-long-instruction-words (VLIWs) used in operations involving the execution of two or more functional units in parallel. Each VLIW comprises a plurality of short-instruction-words (SIWs) where each SIW corresponds to a unique type of instruction associated with a unique functional unit. VLIWs are composed in the VLIW memory by loading and concatenating SIWs in each address, or entry. VLIWs are executed via the execute-VLIW (XV) instruction. The iVLIWs can be compressed at a VLIW memory address by use of a mask field contained within the XV1 instruction which specifics which functional units are enabled, or disabled, during the execution of the VLIW. The mask can be changed each time the XV1 instruction is executed, effectively modifying the VLIW every time it is executed. The VLIW memory (VIM) can be further partitioned into separate memories each associated with a function decode-and-execute unit. With a second execute VLIW instruction XV2, each functional unit'"'"'s VIM can be independently addressed thereby removing duplicate SIWs within the functional unit'"'"'s VIM. This provides a further optimization of the VLIW storage thereby allowing the use of smaller VLIW memories in cost sensitive applications.
-
Citations
22 Claims
-
1. An indirect very long instruction word (VLIW) processor comprising
a plurality of execution units capable of performing a plurality of distinct operations in parallel; -
a VLIW memory (VIM) for storing VLIWs;
an execute VLIW (XNV instruction containing an offset value; and
an addressing mechanism for providing access to each memory entry in VIM, said memory entries each containing at least one instruction slot associated with a unique execution unit, said addressing mechanism comprising a base address register and adder employed in connection with each processing element operable to generate a VIM address by performing a base plus offset calculation utilizing the offset value from the XV instruction for each VLIW access. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 10, 11, 12)
-
-
9. An indirect very long instruction word (VLIW) processor comprising
a plurality of execution units capable of performing a plurality of distinct operations in parallel; -
a VLIW memory (VIM) for storing VLIWs, said VIM being divided into separate VIM sections each of which is associated with one of said plurality of execution units, said VIM sections storing instructions in each of the memory entry slots;
an execute VLIW (XV) instruction containing an offset value; and
an addressing mechanism for each of said VIM sections providing access to each memory entry, in it associated VIM section independently, said addressing mechanism comprising a base address register and adder employed in connection with each processing element operable to generate a VIM address by performing a base plus offset calculation utilizing the offset value from the XV instruction for each VLIW access. - View Dependent Claims (13, 14)
-
-
15. A single instruction multiple data stream (SIMD) processor with a sequence processor (SP) and a plurality of processing elements (PEs), the SP and each PE comprising:
-
a plurality of execution units capable of performing a plurality of distinct operations in parallel;
a very long, instruction word (VLIW) memory (VIM) for storing VLIWs;
an execute VLIW (XV) instruction containing an offset value; and
an addressing mechanism for said VIM providing access to each memory entry in VIM, said memory entries each containing at least one instruction slot associated with a unique execution unit and at least one state bit associated with each instruction slot, designating whether an instruction is available-for-execution or not-available-for-execution, said addressing mechanism comprising a base address register and adder employed in connection with each processing clement operable to generate a VIM address by performing a base plus offset calculation utilizing the offset value from the XV instruction for each VLIW access. - View Dependent Claims (16, 17)
an instruction to execute VLIWs stored in VIM, said instruction containing a field to specify a VIM address, said instruction containing at least one mask bit to control the enabling or disabling of an execution unit at VLIW-instruction-execution-time.
-
-
17. The SIMD processor of claim 15 in which a plurality of different VLIW operations are packed into a single VLIW memory entry so that a plurality of programs can share a single VLIW memory entry.
-
18. A single instruction multiple data stream (SIMD) processor with a sequence processor (SP) and a plurality of processing elements (PEs), the SP and each PE comprising:
-
a plurality of execution units capable of performing a plurality of distinct operations in parallel;
a very long instruction word (VLIW) memory (VIM) for storing VLIWs, said VIM being divided into separate VIM sections each of which is associated with one of said plurality of execution units, said VIM sections storing instructions in each of the memory entry slots;
an execute VLIW (XV) instruction containing an offset value; and
an addressing mechanism for each of said VIM sections providing access to each memory entry, in it associated VIM section independently, said addressing mechanism comprising a base address register and adder employed in connection with each processing element operable to generate a VIM address by performing a base plus offset calculation utilizing the offset value from the XV instruction for each VLIW access. - View Dependent Claims (19, 20, 21, 22)
-
Specification