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Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor

  • US 6,173,389 B1
  • Filed: 12/04/1998
  • Issued: 01/09/2001
  • Est. Priority Date: 12/04/1997
  • Status: Expired due to Term
First Claim
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1. An indirect very long instruction word (VLIW) processor comprisinga plurality of execution units capable of performing a plurality of distinct operations in parallel;

  • a VLIW memory (VIM) for storing VLIWs;

    an execute VLIW (XNV instruction containing an offset value; and

    an addressing mechanism for providing access to each memory entry in VIM, said memory entries each containing at least one instruction slot associated with a unique execution unit, said addressing mechanism comprising a base address register and adder employed in connection with each processing element operable to generate a VIM address by performing a base plus offset calculation utilizing the offset value from the XV instruction for each VLIW access.

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