Real-time power conservation for electronic device having a processor

• US 6,173,409 B1
• Filed: 09/08/1999
• Issued: 01/09/2001
• Est. Priority Date: 10/30/1989
• Status: Expired due to Fees

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Watts, LaVaughn F. Jr., Wallace, Steven J.
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US09/392,205
• Time in Patent Office: 489 Days
• Field of Search: 713/322, 713/601, 713/320, 713/300, 713/600
• US Class Current: 713/322
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A real-time power conservation apparatus and method for portable computers employs a monitor to determine whether a CPU may rest based upon a real-time sampling of the CPU activity level and to activate a hardware selector to carry out the monitor'"'"'s determination. If the monitor determines the CPU may rest, the hardware selector reduces CPU clock time; if the CPU is to be active, the hardware selector returns the CPU to its previous high speed clock level. Switching back into full operation from its rest state occurs without a user having to request it and without any delay in the operation of the computer while waiting for the computer to return to a “ready” state. Furthermore, the monitor adjusts the performance level of the computer to manage power conservation in response to the real-time sampling of CPU activity. Such adjustments are accomplished within the CPU cycles and do not affect the user'"'"'s perception of performance and do not affect any system application software executing on the computer.

Claims

1. An apparatus, comprising:

a central processing unit (CPU) having a monitor for measuring the relative amount of idle time within said CPU; and

a clock manager coupled to said CPU, said clock manager selectively modifying a clock signal being sent to said CPU.

2. An apparatus, comprising:

a central processing unit (CPU) having a monitor for measuring the relative amount of idle time within said CPU; and

a clock manager coupled to said CPU, said clock manager selectively modifying a clock signal being sent to said CPU in response to usage of said CPU being below a preselected level.

3. An apparatus, comprising:

a central processing unit (CPU) having a monitor for measuring the relative amount of idle time within said CPU; and

a clock manager coupled to said CPU, said clock manager selectively modifying a clock signal being sent to said CPU to reduce the idle time in said CPU.

4. The apparatus of claim 3, wherein said monitor inhibits the modification of said clock signal while said CPU is processing critical I/O.

5. The apparatus of claim 3, wherein said CPU sends signals to the clock manager requesting the clock manager to demodify the clock signal being sent to the CPU in response to said monitor detecting a critical I/O request.

6. The apparatus of claim 3, wherein said monitor is self-tuning.

7. The apparatus of claim 6, wherein said monitor uses a control system of continuous feedback loops.

8. An apparatus, comprising:

a central processing unit (CPU) having a monitor for measuring the relative amount of idle time within said CPU; and

a clock manager coupled to said CPU, said clock manager selectively modifying a clock signal being sent to said CPU to minimize the relative amount of idle time in said CPU.

9. An apparatus, comprising:

a central processing unit (CPU) having a monitor for measuring the relative amount of activity time within said CPU; and

a clock manager coupled to said CPU, said clock manager selectively modifying a clock signal being sent to said CPU.

10. The apparatus of claim 9, wherein said monitor inhibits the modification of said clock signal while said CPU is processing critical I/O.

11. The apparatus of claim 9, wherein said CPU sends signals to the clock manager requesting the clock manager to demodify the clock signal being sent to the CPU in response to said monitor detecting a critical I/O request.

12. The apparatus of claim 9, wherein said monitor is self-tuning.

13. The apparatus of claim 12, wherein said monitor uses a control system of continuous feedback loops.

14. An apparatus, comprising:

a central processing unit (CPU) having a monitor for measuring the relative amount of activity time within said CPU; and

a clock manager coupled to said CPU, said clock manager selectively modifying a clock signal being sent to said CPU in response to usage of said CPU being below a preselected level.

15. An apparatus, comprising:

a central processing unit (CPU) having a monitor for measuring the relative amount of activity time within said CPU; and

a clock manager coupled to said CPU, said clock manager selectively modifying a clock signal being sent to said CPU to control the amount of activity time in said CPU.

16. An apparatus, comprising:

a central processing unit (CPU) having a monitor for measuring the relative amount of activity time within said CPU; and

a clock manager coupled to said CPU, said clock manager selectively modifying a clock signal being sent to said CPU to optimize the activity time within said CPU in response to usage of said CPU being below a preselected level.

17. An apparatus, comprising:

a central processing unit (CPU) having a monitor for measuring the relative amount of idle time and activity time within said CPU; and

a clock manager coupled to said CPU, said clock manager selectively modifying a clock signal being sent to said CPU.

18. An apparatus, comprising:

a central processing unit (CPU) having a monitor for measuring the relative amount of idle time and activity time within said CPU; and

a clock manager coupled to said CPU, said clock manager selectively modifying a clock signal being sent to said CPU in response to usage of said CPU being below a preselected level.

19. An apparatus, comprising:

a central processing unit (CPU) having a monitor for measuring the relative amount of idle time and activity time within said CPU; and

a clock manager coupled to said CPU, said clock manager selectively modifying a clock signal being sent to said CPU to control the amount of idle time and activity time in said CPU.

20. The apparatus of claim 19, wherein said monitor inhibits the modification of said clock signal while said CPU is processing critical I/O.

21. The apparatus of claim 19, wherein said CPU sends signals to the clock manager requesting the clock manager to demodify the clock signal being sent to the CPU in response to said monitor detecting a critical I/O request.

22. The apparatus of claim 19, wherein said monitor is self-tuning.

23. The apparatus of claim 22, wherein said monitor uses a control system of continuous feedback loops.

24. An apparatus, comprising:

a central processing unit (CPU) having a monitor for measuring the relative amount of idle time and activity time within said CPU; and

a clock manager coupled to said CPU, said clock manager selectively modifying a clock signal being sent to said CPU to control the amount of idle time and activity time in said CPU in response to a utilization percentage of said CPU being below a preselected level.

25. An apparatus, comprising:

a central processing unit (CPU) having a monitor for measuring the utilization of said CPU; and

a clock manager coupled to said CPU, said clock manager selectively modifying a clock signal being sent to said CPU to control a utilization percentage of said CPU.

26. An apparatus, comprising:

a central processing unit (CPU) coupled to a clock and having a monitor for measuring the relative amount of idle time and activity time within said CPU; and

a clock manager coupled to said CPU, said clock manager controlling periods of time said clock is in an OFF state, the length of said periods of time said clock is in an OFF state being appropriate to allow said CPU to operate at an efficient utilization percentage.

27. The apparatus of claim 26, wherein energy consumption in said CPU is at a maximum when the length of each period of time said clock is in an OFF state is at zero.

28. The apparatus of claim 26, wherein energy consumption in said CPU decreases as the length of each period of time said clock is in an OFF state increases.

29. The apparatus of claim 26, wherein said periods of time said clock is in an OFF state are constantly being adjusted to optimize said utilization percentage of said central processing unit.

30. The apparatus of claim 26, wherein said OFF state represents the minimum clock rate at which said central processing unit can operate.

31. The apparatus of claim 26, wherein said minimum clock rate may be zero for central processing units that can have their clocks stopped.