Apparatus for providing error correction data in a digital data transfer system
First Claim
1. An apparatus for providing error correction data in a digital data transfer system, said apparatus comprising:
- means for receiving a clock signal;
means for providing a first signal using the clock signal;
means for receiving information data;
means for providing a second signal using the information data;
memory means for holding values, said memory means having a plurality of addressable memory locations, each memory location containing a value;
means for addressing said memory means using the first signal to provide a first address component and using the second signal to provide a second address component; and
mathematics means for performing mathematics utilizing a value from said memory means to generate error correction data.
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Accused Products
Abstract
The present invention provides an apparatus for providing error correction data in a digital data transfer system. The apparatus receives a clock signal and provides a first signal using the clock signal. Information data is received and a second signal is provided using the information data. The information data is received in groups which each have a first predetermined number of elements. A plurality of αROMs provide Galois Field multiples in look-up tables. The αROMs are addressed using the first signal to provide a first address component and using the second signal to provide a second address component. Modula mathematics are performed utilizing the values from the αROMs to generate error correction data. The error correction data is in groups each having a second predetermined number of elements. A RAM is accessible by a Trellis encoder and has an array for holding the information data elements and error correction data elements. The number of array locations is equal to an integer multiple of the sum of the first and second predetermined numbers. Further, the information and error correction data elements are sent to the RAM in third groups. A first array location always receives a first element of one of the third groups of data. Thus, the data is easily interleaved by the Trellis encoder.
32 Citations
57 Claims
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1. An apparatus for providing error correction data in a digital data transfer system, said apparatus comprising:
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means for receiving a clock signal;
means for providing a first signal using the clock signal;
means for receiving information data;
means for providing a second signal using the information data;
memory means for holding values, said memory means having a plurality of addressable memory locations, each memory location containing a value;
means for addressing said memory means using the first signal to provide a first address component and using the second signal to provide a second address component; and
mathematics means for performing mathematics utilizing a value from said memory means to generate error correction data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. An apparatus for providing error correction data in a digital data transfer system, said apparatus comprising:
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means for receiving information data, the information data being received in groups which each have a first predetermined number of elements;
means for generating error correction data in response to the information data, the error correction data being in groups each having a second predetermined number of elements; and
memory means, accessible by a portion of said digital data transfer system other than said apparatus, for holding the information data elements and the error correction data elements, said accessible memory means including memory array means having a plurality of array locations, each array location for holding an element, the number of array locations being equal to an integer multiple of the sum of the first and second predetermined numbers. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. An apparatus for providing error correction data in a digital data transfer system, said apparatus comprising:
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means for receiving a clock signal;
means for providing clock-based signals using the clock signal;
means for receiving information data elements in first groups;
means for generating error correction data elements using the information data elements and a clock-based signal from said means for providing clock-based signals, the error correction data elements being in second groups;
memory means, including memory array means having a plurality of array locations, for holding the information data elements and the error correction data elements;
means for sending information data and error correction data elements to said accessible memory means in third groups; and
means for controlling said means for sending in response to a clock-based signal from said means for providing clock-based signals to cause a first array location of said memory array means to always receive a first element of one of the third groups of the information data and error correction data. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40)
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41. An encoder that provides error correction data in a digital data transfer system, said encoder comprising:
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a memory that holds values, said memory has a plurality of addressable memory locations, each memory location contains a value;
a modula counter and register array that performs mathematics utilizing values from said memory to generate error correction data;
at least one counter that receives a clock signal and that provides a first signal using the clock signal;
a data register that receives information data; and
a modula add device that interacts with said modula counter and register array and that uses the information data to provide a second signal; and
whereinsaid memory is addressed using the first signal to provide a first address component and using the second signal to provide a second address component. - View Dependent Claims (42, 43, 44, 45, 46, 47, 48, 49, 50)
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51. An encoder that provides error correction data in a digital data transfer system, said encoder comprising:
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a data register that receives information data, the information data being received in groups which each have a first predetermined number of elements;
a modula counter and register array that generates error correction data in response to the information data, the error correction data being in groups each having a second predetermined number of elements; and
an accessible memory, accessible by a portion of said digital data transfer system other than said encoder, holds the information data elements and the error correction data elements, said accessible memory has a plurality of array locations, each array location holding an elements, the number of array locations being equal to an integer multiple of the sum of the first and second predetermined numbers. - View Dependent Claims (52, 53, 54, 55, 56)
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57. An encoder for providing error correction data in a digital data transfer system, said encoder comprising:
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a counter device that receives a clock signal and that provides clock-based signals using the clock signal;
a data register that receives information data elements in first groups;
a modula counter and register array that generates error correction data elements using the information data elements and a clock-based signal, the error correction data elements being in second groups;
a memory that has a plurality of array locations that hold the information data elements and the error correction on data elements;
a multiplexor that sends information data and error correction data elements to said memory in third groups; and
a selector that controls said multiplexor in response to a clock-based signal to cause a first array location of said memory to always receive a first element of one of the third groups of the information data and error correction data.
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Specification