Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines

• US 6,174,743 B1
• Filed: 12/08/1998
• Issued: 01/16/2001
• Est. Priority Date: 12/08/1998
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Ngo, Minh Van, Besser, Paul R., Pangrle, Suzette K.
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Kielin, Erik J
• Application Number:
  US09/208,623
• Time in Patent Office: 770 Days
• Field of Search: 438/114, 438/622, 438/792, 438/786, 118/715, 427/578, 427/579
• US Class Current: 438/14
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/3145 formed by deposition from a gas or vapour
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing

Abstract

In a method for forming an interlayer dielectric (ILD) coating on microcircuit interconnect lines of a substrate, a SiON layer is formed by using plasma-enhanced chemical vapor deposition. The deposition using a plasma formed of nitrogen, nitrous oxide, and silane gases, with the gases being dispensed at regulated flow rates and being energized by a radio frequency power source. The plasma reacts to form SiON which is deposited on a semiconductor substrate. During deposition, silane flow rates are regulating and reducing to less than sixty standard cubic centimeters per minute, thereby reducing the incidence of stress-induced voiding in the underlying interconnect lines. During deposition adjustments are made in deposition temperature and process pressure to control the characteristics of the SiON layer. The SiON layer is tested for acceptable optical properties and acceptable SiON layers are coated with a SiO₂ layer to complete formation of the ILD. Once the ILD is formed the substrate is in readiness for further processing.

Claims

1. A submicron semiconductor technology process for minimizing thermal stress-induced voids in electrical interconnect line structures, said process comprising the steps of:

a) providing at least one semiconductor substrate having a plurality of transistor gate structures, each transistor gate structure of said plurality of transistor gate structures having a width less than or equal to 0.25 μ

m, and also having at least one pattern of electrical interconnect line structure formed thereon with a line spacing less than 0.35 μ

m;

b) preventing said interconnect line structure from experiencing yield stress due to restricted plastic deformation and to hydrogen embrittlement, and thereby minimizing thermal stress-induced voids in said electrical interconnect line structure by processing said at least one semiconductor substrate via a process selected from a group of processes consisting essentially of

(1) setting PECVD deposition parameters comprising a deposition temperature in a range greater than 200 to 400 degrees Celsius (°

C.), setting a chamber pressure, a plurality of gas flow rates for producing an NH₃-free plasma, and a plasma-energizing power setting for producing a silicon oxynitride layer having a refractive index in a target range of 1.63 and 1.71, and then depositing a silicon oxynitride layer between and on top of said electrical interconnect line structure using PECVD techniques,

whereby said depositing step includes forming said NH₃-free plasma comprising nitrogen, nitrous oxide, and silane gases being dispensed at said set flow rates and being energized at said set plasma-energizing power setting by a radio frequency power source,

whereby said silane gas flow rate is less than 60 standard cubic centimeters per minute,

whereby the ratio of said silane gas flow rate to said nitrous oxide gas flow rate is maintained at approximately 1;

1 for minimizing hydrogen embrittlement, thereby facilitating the minimization of said stress-induced voids,

whereby during a deposition heating period, said electrical interconnect line structure does not experience a yield stress and, therefore, is not plastically deformed,

whereby during a post-deposition cooling period, minimization of thermal stress-induced voids is effected in said electrical interconnect line structure,

whereby said depositing step comprises adjusting a combination of said energizing-power setting and said chamber pressure to yield said silicon oxynitride layer having said refractive index in said refractive index target range, and

whereby said energizing-power setting and said chamber pressure are adjusted in a range of 285-330 W and in a range of 2.5-6.0 Torr, respectively, and

(2) setting PECVD deposition parameters comprising a deposition temperature in a range greater than 200 to 380 degrees Celsius (°

C.) for facilitating a minimization of thermal stress-induced voids during post-deposition cooling of said interconnect line structures, and further setting a chamber pressure, a plurality of gas flow rates for producing an NH₃-free plasma, and a plasma-energizing power setting for producing a silicon oxynitride layer having a refractive index in a target range of 1.63 and 1.71, and then depositing a silicon oxynitride layer between and on top of said electrical interconnect line structure using PECVD techniques,

whereby said depositing step includes forming said NH₃-free plasma comprising nitrogen, nitrous oxide, and silane gases being dispensed at said set flow rates and being energized at said set plasma-energizing power setting by a radio frequency power source,

whereby said nitrogen gas flow rate is set at approximately 2000 standard cubic centimeters per minute,

whereby said silane gas flow rate is set less than 60 standard cubic centimeters per minute,

whereby the ratio of said nitrous oxide gas flow rate to said silane gas flow rate is maintained at approximately 1;

1 for minimizing hydrogen embrittlement, thereby facilitating said minimization of said stress-induced voids,

whereby said set gas flow rates facilitate producing said silicon oxynitride layer having said refractive index in said target range of 1.63 to 1.71;

whereby during a deposition heating period, said electrical interconnect line structure does not experience a yield stress and, therefore, is not plastically deformed,

whereby during a post-deposition cooling period, minimization of thermal stress-induced voids is effected in said electrical interconnect line structure,

whereby said depositing step comprises adjusting a combination of said energizing-power setting and said chamber pressure to yield said silicon oxynitride layer having said refractive index in said refractive index target range, and

whereby said energizing-power setting and said chamber pressure are adjusted in a range of 285-330 W and in a range of 2.5-6.0 Torr, respectively;

c) testing said silicon oxynitride layer and determining that its refractive index is in said refractive index target range; and

d) depositing a layer of silicon dioxide on top of said silicon oxynitride layer to complete the formation of an interlayer dielectric.

2. A submicron semiconductor technology process, as recited in claim 1, wherein said silane gas flow rate is in a range of approximately greater than 45 and less than 60 standard cubic centimeters per minute and the ratio of said silane gas flow rate to said nitrous oxide gas flow rate is maintained at approximately 1:

1 for minimizing hydrogen embrittlement, thereby minimizing said stress-induced voids.

3. A submicron semiconductor technology process, as recited in claim 1, wherein said depositing step comprises adjusting said energizing-power setting and said chamber pressure to yield said silicon oxynitride layer having said refractive index in said refractive index target range.

4. A submicron semiconductor technology process, as recited in claim 3, wherein said energizing-power setting and said chamber pressure are adjusted in a range of 285-330 W and in a range of 2.5-6.0 Torr, respectively.

5. A submicron semiconductor technology process, as recited in claim 1, wherein said electrical interconnect line structures comprise at least one layer of aluminum containing material.

6. A submicron semiconductor technology process, as recited in claim 1, wherein said electrical interconnect line structures comprise at least one layer of copper containing material.