Salicide device with borderless contact

• US 6,174,762 B1
• Filed: 03/02/1999
• Issued: 01/16/2001
• Est. Priority Date: 03/02/1999
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Radens, Carl J., Bronner, Gary B., Hsu, Louis L., Gambino, Jeffrey P., Tonti, William R., Mandelman, Jack A.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): POMPEY, RON EVERETT
• Application Number:
  US09/260,311
• Time in Patent Office: 686 Days
• Field of Search: 438/592, 438/595, 438/230, 257/413
• US Class Current: 438/230
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

A method and structure for a field effect transistor structure for dynamic random access memory integrated circuit devices has a gate conductor, salicide regions positioned along sides of the gate conductor, a gate cap positioned above the gate conductor and at least one self-aligned contact adjacent the gate conductor.

Claims

1. A method of manufacturing a field effect transistor structure in a dynamic random access memory integrated circuit device comprising:

forming an insulator over a gate conductor and a gate cap;

etching said insulator to form spacers along a lower portion of sides of said gate conductor;

forming a metal over said gate conductor, said gate cap and said spacers;

heating said metal to form salicide regions along upper portions of said sides of said gate conductor in direct contact with said metal;

removing said metal and leaving said salicide regions; and

forming at least one self-aligned contract adjacent said gate conductor.

2. The method in claim 1, wherein said etching comprises over-etching said insulator such that said upper portions of said sides of said gate conductor are exposed and come into direct contact with said metal.

3. The method in claim 1, wherein said heating includes forming salicide regions above a source region and above a drain region of said field effect transistor.

4. The method in claim 1, wherein said step of forming said self-aligned contact includes making an electrical connection to one of a source region and a drain region of said field effect transistor.

5. A method of manufacturing an integrated circuit device comprising:

forming spacers along a lower portion of sides of a conductor by forming an. insulator over said conductor and a cap of said conductor, and etching said insulator to form said spacer along said lower portion of said sides of said conductor;

forming salicide regions along upper portions of said sides of said conductor; and

forming at least one self-aligned contact adjacent said conductor.

6. The method in claim 5, wherein said forming of said salicide regions comprises:

Forming a metal over said conductor, a cap of said conductor, and said spacers; and

heating said metal to form salicide regions along upper portions of said sides of said conductor in direct contact with said metal.

7. The method in claim 5, wherein said etching comprises over-etching said spacers such that said upper portions of said sides of said gate conductor are exposed and come into direct contact with said metal.

8. The method in claim 5, wherein said forming of said salicide regions includes forming salicide regions above a source region and a drain region of said field effect transistor.