Method for manufacturing stacked capacitor

• US 6,174,769 B1
• Filed: 06/18/1999
• Issued: 01/16/2001
• Est. Priority Date: 04/27/1999
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Worldwide Semiconductor Manufacturing Corp.
• Inventors: Lou, Chine-Gie
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Thomas, Toniae M.
• Application Number:
  US09/335,547
• Time in Patent Office: 578 Days
• Field of Search: 438/238, 438/239, 438/253, 438/254, 438/255, 438/396, 438/397, 438/398
• US Class Current: 438/253
• CPC Class Codes: H01L 28/82 with an enlarged surface, e.g. formed by texturisation
• CPC Class Codes: H01L 28/84 being a rough surface, e.g. using hemispherical grains
• CPC Class Codes: H01L 28/87 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor

Abstract

A method for manufacturing stacked capacitor. The method utilizes a manufacture method of a trench line and a via applied in dual damascene process to form a trench line and a via in a dielectric layer. Then, multi-amorphous silicon layers with different doping concentration are conformally formed on an exposed surface of the trench line and the via to serve as a bottom electrode of a double-sided double-crown-shaped capacitor. Furthermore, a phosphine (PH₃) treatment process is performed after hemispherical grains are formed on the bottom electrode of the double-sided double-crown-shaped capacitor to increase the doping concentration of the bottom electrode surface of the capacitor. Moreover, a poly slurry having a high polishing selectivity of amorphous silicon to silicon nitride is used in a chemical mechanical polishing process during the formation of the double-sided double-crown-shaped capacitor to promote good uniformity of the polished wafer and make the polish end point available.

Claims

1. A method for manufacturing a stacked capacitor, comprising the steps of:

providing a substrate;

forming a first dielectric layer over the substrate;

forming a contact opening in the first dielectric layer. wherein a depth of the contact opening is substantially equal to a thickness of the first dielectric layer;

forming a conductive plug inside the contact opening;

forming a second dielectric layer on the first dielectric layer that covers the conductive plug also;

forming a trench line in a top portion of the second dielectric layer;

forming a via in a bottom portion of the second dielectric layer beneath the trench line to expose the conductive plug and a portion of the first dielectric layer abutting the conductive plug;

forming an undoped first amorphous silicon layer on the second dielectric layer, conformal to a peripheral surface of the trench line and the via;

forming a doped second amorphous silicon layer on and conformal to the undoped first amorphous silicon layer;

forming an undoped third amorphous silicon layer on and conformal to the doped second amorphous silicon layer;

forming a photoresist layer over the substrate to fill the trench line and the via in the second dielectric layer;

polishing the photoresist layer, the undoped third amorphous silicon layer, the doped second amorphous silicon layer and the undoped first amorphous silicon layer to expose the second dielectric layer using the second dielectric layer as a polishing stop layer;

removing the photoresist layer filling in the trench line and the via;

removing the second dielectric layer;

forming a plurality of hemispherical grains over an exposed surface of the undoped first amorphous silicon layer, the doped second amorphous silicon layer and the undoped third amorphous silicon layer; and

performing a doping process to the hemispherical grains, the undoped first amorphous silicon layer and the undoped third amorphous silicon layer.

2. The method of claim 1, wherein the second dielectric layer includes a first silicon nitride layer, a first silicon oxide layer, a second silicon nitride layer, a second silicon oxide layer and a third silicon nitride layer.

3. The method of claim 2, wherein the trench line is formed in the second silicon oxide layer and the third silicon nitride layer using the second silicon nitride layer as a etching stop layer.

4. The method of claim 2, wherein the via is formed in the first silicon nitride layer, the first silicon oxide layer and the second silicon nitride layer using the first dielectric layer as a etching stop layer.

5. The method of claim 1, wherein the doped second amorphous silicon layer has a doping concentration preferably around 6E20 ions/cm³.

6. The method of claim 1, wherein the photoresist layer, the undoped third amorphous silicon layer, the doped second amorphous silicon layer and the undoped first amorphous silicon layer above the second dielectric layer are removed by chemical mechanical polishing method.

7. The method of claim 6, wherein a poly slurry used in the chemical mechanical polishing method has a high polishing selectivity of amorphous silicon to silicon nitride.

8. The method of claim 1, wherein the doping process includes a phosphine (PH₃) treatment process.

9. The method of claim 8, wherein the phosphine (PH₃) treatment process is performed for about 5 to 30 minutes with a phosphine (PH₃) gas pressure of around 1 to 10 torr and at a temperature of between about 700°

C. to 750°

C.

10. A method for manufacturing a stacked capacitor, comprising the steps of:

providing a substrate having a number of devices and a conductive plug formed thereon;

forming a dielectric layer over the substrate;

forming a trench line and a via beneath the trench line in the dielectric layer to expose the conductive plug, wherein a portion of the substrate abutting the conductive plug is exposed also;

forming an undoped first amorphous silicon layer over the dielectric layer conformal to the trench line and the via;

forming a doped second amorphous silicon layer on and conformal to the undoped first amorphous silicon layer;

forming an undoped third amorphous silicon layer on and conformal to the doped second amorphous silicon layer;

forming a photoresist layer over the substrate to fill the trench line and the via;

polishing the photoresist layer, the undoped third amorphous silicon layer, the doped second amorphous silicon layer and the undoped first amorphous silicon layer to expose the dielectric layer using the dielectric layer as a polishing stop layer;

removing the photoresist layer filling in the trench line and the via;

removing the dielectric layer;

forming a plurality of hemispherical grains over an exposed surface of the undoped first amorphous silicon layer, the doped second amorphous silicon layer, and the undoped third amorphous silicon layer; and

performing a doping process to the hemispherical grains, the undoped first amorphous silicon layer and the undoped third amorphous silicon layer. a doping process to the hemispherical grains, the undoped first amorphous silicon layer and the undoped third amorphous silicon layer.

11. The method of claim 10, wherein the dielectric layer includes a first silicon nitride layer, a first silicon oxide layer, a second silicon nitride layer, a second silicon oxide layer and a third silicon nitride layer.

12. The method of claim 11, wherein the trench line is formed in the second silicon oxide layer and the third silicon nitride layer using the second silicon nitride layer as a etching stop layer.

13. The method of claim 11, wherein the via is formed in the first silicon nitride layer, the first silicon oxide layer and the second silicon nitride layer.

14. The method of claim 10, wherein the doped second amorphous silicon layer has a doping concentration preferably around 6E20 ions/cm³.

15. The method of claim 10, wherein the photoresist layer, the undoped third amorphous silicon layer, the doped second amorphous silicon layer and the undoped first amorphous silicon layer above the dielectric layer are removed by chemical mechanical polishing method.

16. The method of claim 15, wherein a poly slurry used in the chemical mechanical polishing method has a high polishing selectivity of amorphous silicon to silicon nitride.

17. The method of claim 10, wherein the doping process includes a phosphine (PH₃) treatment process.

18. The method of claim 17, wherein the phosphine (PH₃) treatment process is performed for about 5 to 30 minutes with a phosphine (PH₃) gas pressure of around 1 to 10 torr and at a temperature of between about 700°

C. to 750°

C.

19. A method-for manufacturing a stacked capacitor, comprising the steps of:

providing a substrate;

forming a first dielectric layer over the substrate;

forming a contact opening in the first dielectric layer, wherein a depth of the contact opening is substantially equal to a thickness of the first dielectric layer;

forming a conductive plug inside the contact opening;

sequentially forming a first silicon nitride layer, a first oxide layer, a second silicon nitride layer, a second oxide layer, and a third silicon nitride layer on the substrate, wherein the first silicon nitride layer, the first oxide layer, and the second silicon nitride layer serves together as a lower dielectric layer, and the second oxide layer and the third silicon nitride layer serves together as an upper dielectric layer;

patterning the upper dielectric layer to form a trench that exposes a portion of the lower dielectric layer;

patterning the exposed portion of the lower dielectric layer to form a via that at least exposes the conductive plug;

forming an undoped first amorphous silicon layer over the substrate, conformal to a topographic surface of the substrate, including a peripheral surface of the trench and the via;

forming a doped second amorphous silicon layer on and conformal to the undoped first amorphous silicon layer;

forming an undoped third amorphous silicon layer on and conformal to the doped second amorphous silicon layer;

forming a photoresist layer over the substrate to fill the trench and the via in the lower dielectric layer and the upper dielectric layer;

polishing the photoresist layer, the undoped third amorphous silicon layer, the doped second amorphous silicon layer and the undoped first amorphous silicon layer to expose the third silicon nitride layer of the upper dielectric layer that also serves as a polishing stop layer;

removing the photoresist layer filling in the trench and the via;

removing the second dielectric layer;

forming a plurality of hemispherical grains over an exposed surface of the undoped first amorphous silicon layer, the doped second amorphous silicon layer and the undoped third amorphous silicon layer; and

performing a doping process to the hemispherical grains, the undoped first amorphous silicon layer and the undoped third amorphous silicon layer.