Method of manufacturing vertical trench misfet

• US 6,174,773 B1
• Filed: 08/27/1999
• Issued: 01/16/2001
• Est. Priority Date: 02/17/1995
• Status: Expired due to Term

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Fujishima, Naoto
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Thompson, Craig
• Application Number:
  US09/384,156
• Time in Patent Office: 508 Days
• Field of Search: 438/270, 438/271-272, 438/197, 438/302
• US Class Current: 438/270
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A vertical trench MISFET is provided that includes a semiconductor substrate having a first conductivity type semiconductor, and a second conductivity type impurity layer provided on the first conductivity type semiconductor. A trench extends from a surface of the semiconductor substrate to reach said first conductivity type semiconductor. A second conductivity type base region is formed in a top portion of the semiconductor substrate, and a first conductivity type source region is formed in a part of a surface layer of the second conductivity type base region. A first conductivity type drain drift region having a small thickness is formed in a surface layer of a side wall of the trench. The drain drift region has a higher impurity concentration than a level at which a breakdown voltage measured in a hypothetical diffusion type junction is substantially equal to an element withstand voltage. A gate electrode is formed on an exposed surface of the second conductivity type base region, through a gate insulating film. A source electrode is disposed in contact with surfaces of both of the first conductivity type source region and the second conductivity type base region, while a drain electrode is disposed in contact with a rear surface of the first conductivity type semiconductor.

Claims

1. A method of manufacturing a vertical trench MISFET, comprising the steps of:

preparing a semiconductor substrate having a first conductivity type semiconductor, and a second conductivity type impurity layer disposed on the first conductivity type semiconductor;

forming a trench extending from a surface of said semiconductor substrate to reach said first conductivity type semiconductor;

forming a second conductivity type base region in a top portion of said semiconductor substrate;

forming a first conductivity type source region in a part of a surface layer of said second conductivity type base region;

forming an impurity diffused layer by obliquely implanting ions into a side wall of said trench, which is then subjected to heat treatment, thereby to form a first conductivity type drain drift region in a surface layer of the side wall of the trench, said first conductivity type drain drift region having a first impurity concentration that is higher than a second impurity concentration at which a breakdown voltage measured in a hypothetical diffusion type junction is substantially equal to an element withstand voltage;

forming a gate electrode on an exposed surface of said second conductivity type base region, through a gate insulating film;

forming a source electrode in contact with surfaces of both of said first conductivity type source region and said second conductivity type base region; and

forming a drain electrode in contact with a rear surface of said first conductivity type semiconductor.

2. A method of manufacturing a vertical trench MISFET, comprising the steps of:

preparing a semiconductor substrate having a first conductivity type semiconductor, and a first conductivity type impurity layer provided on the first conductivity type semiconductor, said first conductivity type impurity layer having a first impurity concentration that is higher than a second impurity concentration at which a breakdown voltage measured in a hypothetical diffusion type junction is substantially equal to an element withstand voltage;

forming a trench extending from a surface of said semiconductor substrate to reach said first conductivity type semiconductor;

forming a second conductivity type base region in a top portion of said semiconductor substrate;

forming a first conductivity type source region in a part of a surface layer of said second conductivity type base region;

forming an impurity diffused layer by obliquely implanting ions into a side wall of said trench, which is then subjected to heat treatment, thereby to form a second conductivity type side wall region in a surface layer of the side wall of the trench;

forming a gate electrode on an exposed surface of said second conductivity type base region, through a gate insulating film;

forming a source electrode in contact with surfaces of both of said first conductivity type source region and said second conductivity type base region; and

forming a drain electrode in contact with a rear surface of said first conductivity type semiconductor.