Integrated circuit device interconnection techniques

• US 6,174,803 B1
• Filed: 09/16/1998
• Issued: 01/16/2001
• Est. Priority Date: 09/16/1998
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Harvey, Ian
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Berezny, Nema
• Application Number:
  US09/154,050
• Time in Patent Office: 853 Days
• Field of Search: 438/622, 438/637, 438/638, 257/758, 257/776
• US Class Current: 438/638
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention relates to multilevel integrated circuit interconnection techniques. An integrated circuit having a number of electronic components along a semiconductor substrate and a first connection layer having a first number of conductors in selective electrical contact with the components is provided. A first insulative layer is formed on the first connection layer with a first pattern of openings therethrough. A second connection layer is established that has a second number of conductors selectively interconnected to the first conductors through the first pattern of openings. A second insulative layer is formed on the first connection layer with a second pattern of openings therethrough. A third connection layer is formed on the second insulative layer having a third dielectric and a third number of conductors selectively interconnecting the second conductors. The first and second insulative layers are preferably etch selective to a dielectric included in the first, second, and third connection layers; and crossover, crossunder, or local interconnects are formed in a different connection layer than routing interconnects to facilitate higher interconnection density.

Claims

1. A method of integrated circuit manufacture, comprising:

providing a number of electronic components along a semiconductor substrate, and a first connection layer comprised of a first dielectric and a first number of conductors in selective electrical contact with the components;

forming a first insulative layer on the first connection layer with a first pattern of openings therethrough;

establishing a second connection layer comprised of a second dielectric and a second number of conductors selectively interconnecting the first conductors through the first pattern of openings;

forming a second insulative layer on the second connection layer with a second pattern of openings therethrough; and

establishing a third connection layer on the second insulative layer comprised of a third dielectric and a third number of conductors selectively interconnecting the second conductors, the third dielectric being etch selective to the second insulative layer, the second and third conductors being in contact with the second insulative layer, and at least one of the second conductors crossing at least one of the third conductors and being electrically isolated therefrom by the second insulative layer.

2. The method of claim 1, wherein the second conductors or the third conductors are each formed as an elongated metal routing interconnect extending over several of the components to route a corresponding long-distance signal.

3. The method of claim 1, wherein at least one of the second conductors is operable to provide a power supply voltage to the components.

4. The method of claim 1, wherein:

the first conductors and the third conductors are formed as elongate metal routing interconnects to extend over several of the components and provide long-distance signal routing; and

the second conductors include at least one crossover connection electrically interconnecting at least two of the first conductors and at least one crossunder connection electrically interconnecting at least two of the third conductors.

5. The method of claim 1, wherein said providing includes:

depositing a coating of the first dielectric over the components;

etching the coating to define a first number of recesses each exposing two contact surfaces of the components; and

depositing a metallic material in the first recesses to form a corresponding first subset of the first conductors each providing a local interconnection between the two surfaces exposed by a respective one of the first recesses.

6. The method of claim 5, wherein said etching further includes defining a second number of recesses in the coating each exposing a contact surface of a corresponding one of the components and said depositing includes filling the second recesses with the metallic material to provide a corresponding second subset of the first conductors.

7. The method of claim 5, wherein the second conductors include a number of metal plugs and a number of elongate metal routing interconnects each extending over several of the components, the plugs are positioned between the first conductors and the routing interconnects to electrically interconnect the first conductors and the routing interconnects in correspondence with the first pattern of openings, and the second dielectric material is etch selective relative to the first insulative layer.

8. The method of claim 1, wherein the second conductors are formed in recesses defined in the second dielectric material, the second conductors contact the first insulative layer, and the second dielectric is etch selective relative to the first insulative layer.

9. The method of claim 1, wherein said providing includes:

depositing a dielectric coating over the components;

planarizing the dielectric coating after said depositing;

depositing a insulative film on the coating after said planarizing; and

etching the film to define the first pattern of openings;

forming a layer of the first dielectric on the film;

etching the first dielectric and the dielectric coating selective to the film to form a number of recesses, at least a portion of the recesses passing through the first pattern of openings; and

depositing metal in the recesses to form the first conductors.

10. The method of claim 1, wherein:

said forming the first insulative layer includes depositing a dielectric film on the first connection layer and etching the film to define the first pattern of openings; and

said establishing the second connection layer includes covering the first insulative layer with a coating of the second dielectric, etching the coating of the second dielectric to define a number of recesses, and depositing a conductive material in the recesses to provide the second conductors.

11. The method of claim 1, wherein:

said forming the second insulative layer includes depositing a dielectric film on the second connection layer and etching the film to define the second pattern of openings; and

said establishing the third connection layer includes covering the second insulative layer with a coating of the third dielectric, etching the third dielectric to define a number of recesses, and depositing a conductive material in the recesses to provide the third conductors.

12. The method of claim 1, wherein the first, second, and third dielectrics are predominantly composed of silicon dioxide, and the first and second insulative layers are predominantly composed of silicon nitride or silicon oxynitride.

13. A method of integrated circuit manufacture, comprising:

providing a number of electronic components on a substrate;

planarizing a first dielectric layer formed over the components;

forming a first insulative hard mask on the first layer and a second dielectric layer on the first hard mask, a first pattern of openings being defined through the first hard mask;

etching the first and second layer selective to the first hard mask to form a first number of recesses in the second layer, at least a portion of the first recesses being coincident with the first pattern of openings to extend through the first layer;

at least partially filling the first recesses to define a first number of conductors in elective contact with the components through the first pattern of openings;

depositing a second insulative hard mask on the second layer and a third dielectric layer on the second hard mask;

etching the third layer selective to the second hard mask to define a second number of recesses therein;

at least partially filling the second recesses to define a second number of conductors selectively connecting the first conductors through a second pattern of openings in the second hard mask;

depositing a third insulative hard mask on the third layer and a fourth dielectric layer on the third hard mask;

etching the fourth layer selective to the third hard mask to form a third number of recesses therein; and

at least partially filling the third recesses to define a third number of conductors selectively connected by the second conductors through a third pattern of openings in the third hard mask, at least a portion of the first and third conductors being routing interconnects.

14. The method of claim 13, wherein the first layer and the second layer are composed of silicon dioxide and the first hard mask is composed of silicon nitride or silicon oxynitride.

15. The method of claim 13, wherein the third layer is composed of silicon oxide and the second hard mask is composed of silicon nitride or silicon oxynitride.

16. The method of claim 15, wherein the fourth layer is composed of silicon oxide and the third hard mask is composed of silicon nitride or silicon oxynitride.

17. The method of claim 13, wherein the second conductors provide a number of overpass interconnections between the first conductors and a number of underpass interconnections between the third conductors.

18. The method of claim 13, wherein the first and third conductors are all elongate metal routing interconnects extending over several of the components to provide long-distance signal routing.

19. The method of claim 13, wherein the second conductors provide a number of power supply connections.

20. The method of claim 13, wherein the first, second, third, or fourth layers are each etch selective to the first, second, and third hard masks;

and the first, second, and third hard masks are each etch selective to the first, second, third, and fourth layers.

21. A method of integrated circuit manufacture, comprising:

providing a number of electronic components on a substrate;

selectively removing a first dielectric layer deposited over the components to define a first number of recesses each exposing at least two electrical contact surfaces of the components;

at least partially filling each of the recesses in the first layer to provide a corresponding number of local interconnects between the at least two contact surfaces;

forming a first insulative hard mask on the first layer and local interconnects, a second dielectric layer including a first number of conductors over the first hard mask, and a second hard mask over the first conductors, the first conductors being selectively electrically coupled to the components through a first pattern of openings in the first hard mask;

forming a third dielectric layer in contact with the second hard mask;

etching the third layer selective to the second hard mask to form a second number of recesses; and

at least partially filling the second recesses to define a second number of conductors in the third layer selectively connecting the second conductors through a second pattern of openings defined by the second hard mask, the first routing interconnects and the second routing interconnects being in contact with the second hard mask.

22. The method of claim 21, wherein the first layer and the second layer are composed of silicon dioxide, and the first hard mask and the second hard mask are composed of silicon nitride or silicon oxynitride.

23. The method of claim 21, wherein the first conductors include a number of via plugs electrically coupled to the local interconnects in correspondence with the first pattern of openings.

24. The method of claim 23, wherein the first conductors further include a plurality of routing interconnects.