Integrated deposition process for copper metallization
First Claim
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1. A process for forming an interconnect, comprising:
- positioning a patterned substrate into a first high density physical vapor deposition chamber and depositing a barrier layer on the substrate, wherein the barrier layer is selected from the group of tantalum, tantalum nitride, and combinations thereof;
positioning the substrate into a second high density physical vapor deposition chamber and depositing a first copper layer on the barrier layer; and
depositing a second copper layer on the first copper layer;
wherein depositing the barrier layer comprises delivering a bias between about 0.5 kW and about 5 kW to a target, delivering RF power between about 0.5 kW and about 3 kW to a source coil, and delivering a bias between about) W and about 500 W to the substrate.
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Abstract
Metallization process sequences are provided for forming reliable interconnects including lines, vias and contacts. An initial barrier layer, such as Ta or TaN, is first formed on a patterned substrate followed by seed layer formed using high density plasma PVD techniques. The structure is then filled using either 1) electroplating, 2) PVD reflow, 3) CVD followed by PVD reflow, or 4) CVD.
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7 Claims
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1. A process for forming an interconnect, comprising:
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positioning a patterned substrate into a first high density physical vapor deposition chamber and depositing a barrier layer on the substrate, wherein the barrier layer is selected from the group of tantalum, tantalum nitride, and combinations thereof;
positioning the substrate into a second high density physical vapor deposition chamber and depositing a first copper layer on the barrier layer; and
depositing a second copper layer on the first copper layer;
wherein depositing the barrier layer comprises delivering a bias between about 0.5 kW and about 5 kW to a target, delivering RF power between about 0.5 kW and about 3 kW to a source coil, and delivering a bias between about) W and about 500 W to the substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification