Charge pump for generating negative voltage without change of threshold due to undesirable back-gate biasing effect

• US 6,175,264 B1
• Filed: 03/12/1999
• Issued: 01/16/2001
• Est. Priority Date: 03/16/1998
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Jinbo, Toshikatsu
• Primary Examiner(s): Cunningham, Terry D.
• Assistant Examiner(s): TRA, ANH QUAN
• Application Number:
  US09/267,158
• Time in Patent Office: 676 Days
• Field of Search: 327/534, 327/535, 327/536, 327/537, 327/566
• US Class Current: 327/536
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: H02M 3/071 adapted to generate a negative voltage output from a positive voltage source
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H02M 3/075 including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages

Abstract

A boosting stage of a charge pump circuit has a boosting capacitor connected to a boosted node and an n-channel enhancement type field effect transistor connected between the boosted node and other node and fabricated on a p-type well connected to the other node, and the n-channel enhancement type field effect transistor turns on for discharging current from the other node to the boosted node through the conductive channel and the p-n junction between the p-type well and the n-type source node thereof so that the potential level at the p-type well restricts the back-gate biasing effect, thereby widely swinging the potential level at the other node.

Claims

1. A charge pump circuit comprising:

a plurality of nodes independently variable in potential level;

a diode circuit including a first field effect transistor connected between one of said plurality of nodes and a source of constant voltage and having

a diode connected between a back gate and a positive power supply line;

the first back gate also being connected to said one of said plurality of nodes and supplied with a first potential for restricting a back-gate biasing effect in said first field effect transistor and

a first gate electrode connected to said one of said plurality of nodes and responsive to said first potential for creating a first current path from said one of said plurality of nodes to said source of constant voltage; and

a plurality of boosting stages connected in series between said plurality of nodes and responsive to first clock signals for selectively boosting the potentials at said plurality of nodes and selectively discharging said potentials toward said diode circuit, each of said plurality of boosting stages including

a second field effect transistor connected between two nodes selected from said plurality of nodes and having

a second back gate connected to the positive power supply line via a second diode and electrically isolated from said first back gate, connected to one of said two nodes farther from said one of said plurality of nodes than the other of said two nodes and supplied with a second potential independently varied for restricting said back-gate biasing effect in said second field effect transistor and

a second gate electrode connected to said one of said two nodes and responsive to said second potential for creating a second current path from said one of said two nodes to said other of said two nodes, and

a first capacitor connected to said other of said two nodes and responsive to one of said first clock signals for boosting the potential at said other of said two nodes.

2. The charge pump circuit as set forth in claim 1, in which said first field effect transistor and said second field effect transistor are respectively fabricated on a first well opposite in conductivity type to a first conductive channel serving as said first current path and a second well electrically isolated from said first well and opposite in conductivity type to a second conductive channel serving as said second current path, and said first well and said second well serve as said first back gate and said second back gate, respectively.

3. The charge pump circuit as set forth in claim 2, in which said first field effect transistor and said second field effect transistor are operative in an enhancement mode for independently creating said first conductive channel and said second conductive channel both featured by a donor, and a negative voltage is generated at another of said plurality of nodes serving as an output node.

4. The charge pump circuit as set forth in claim 2, in which said first well and said second well form a first p-n junction and a second p-n junction together with a first source region of said first field effect transistor and a second source region of said second field effect transistor, respectively, and said first p-n junction and said second p-n junction are forwardly biased with said first potential and said second potential so that said first well and said second well respectively offer a third current path and a fourth current path in parallel to said first current path and said second current path, respectively.

5. The charge pump circuit as set forth in claim 4, in which said first well and said second well are electrically connected through a first contact region and a second contact region to said one of said plurality of nodes and said one of said two nodes, respectively, and said first field effect transistor and said second field effect transistor are respectively surrounded by said first contact region and said second contact region.

6. The charge pump circuit as set forth in claim 5, in which one of said first and second gate electrodes is bifurcated so as to provided one of said first and second conductive channels between a drain region of one of said first and second field effect transistors and two source sub-regions of one of said first and second source regions formed on both sides of said drain region.

7. The charge pump circuit as set forth in claim 5, in which said first gate electrode is bifurcated so as to provided said first conductive channel between a first drain region of said first field effect transistor and two source sub-regions of said first source region formed on both sides of said first drain region, and said second gate electrode is bifurcated so as to provided said second conductive channel between a second drain region of said second field effect transistor and two source sub-regions of said second source region formed on both sides of said second drain region.

10. The charge pump circuit as set forth in claim 1, in which said each of said plurality of boosting stages further includes

a second capacitor connected to said second gate electrode and responsive to one of second clock signals for periodically boosting a potential level at said second gate electrode, and

a third field effect transistor connected between said second gate electrode and said one of said two nodes and responsive to the potential level at said other of said two nodes for connecting said second gate electrode to said one of said two nodes, a back gate of the third field effect transistor being connected to said one of said two nodes.

11. The charge pump circuit as set forth in claim 10, in which said first field effect transistor, said second field effect transistor and said third field effect transistor are operative in an enhancement mode for creating conductive channels featured by a donor.

14. The charge pump circuit as set forth in claim 3, in which said negative voltage is supplied to an electrically erasable read only memory cell.

8. A charge pump circuit comprising:

a plurality of nodes independently variable in potential level;

a diode circuit including a first field effect transistor connected between one of said plurality of nodes and a source of constant voltage and having

a first back gate connected to said one of said plurality of nodes and supplied with a first potential for restricting a back-gate biasing effect in said first field effect transistor and

a first gate electrode connected to said one of said plurality of nodes and responsive to said first potential for creating a first current path from said one of said plurality of nodes to said source of constant voltage; and

a plurality of boosting stages connected in series between said plurality of nodes and responsive to first clock signals for selectively boosting the potentials at said plurality of nodes and selectively discharging said potentials toward said diode circuit, each of said plurality of boosting stages including

a second field effect transistor connected between two nodes selected from said plurality of nodes and having

a second back gate electrically isolated from said first back gate, connected to one of said two nodes farther from said one of said plurality of nodes than the other of said two nodes and supplied with a second potential independently varied for restricting said back-gate biasing effect in said second field effect transistor and

a second gate electrode connected to said one of said two nodes and responsive to said second potential for creating a second current path from said one of said two nodes to said other of said two nodes, and

a first capacitor connected to said other of said two nodes and responsive to one of said first clock signals for boosting the potential at said other of said two nodes in which said first field effect transistor and said second field effect transistor are respectively fabricated on a first well opposite in conductivity type to a first conductive channel serving as said first current path and a second well electrically isolated from said first well and opposite in conductivity type to a second conductive channel serving as said second current path, and said first well and said second well serve as said first back gate and said second back gate, respectively,

in which said first well and said second well are formed in a first surface portion and a second surface portion of a third well opposite in conductivity type to said first and second wells and spaced from each other, said third well is formed in a surface portion of a semiconductor substrate, and p-n junctions between said first and second wells and said third well are reversely biased.

9. The charge pump circuit as set forth in claim 8, in which a channel stopper is formed in said third well in such a manner as to surround said first well and said second well for restricting a surface leakage current from said first and second wells to said semiconductor substrate.

12. A charge pump circuit comprising:

a plurality of nodes independently variable in potential level;

a diode circuit including a first field effect transistor connected between one of said plurality of nodes and a source of constant voltage and having

a first back gate connected to said one of said plurality of nodes and supplied with a first potential for restricting a back-gate biasing effect in said first field effect transistor and

a first gate electrode connected to said one of said plurality of nodes and responsive to said first potential for creating a first current path from said one of said plurality of nodes to said source of constant voltage; and

a plurality of boosting stages connected in series between said Plurality of nodes and responsive to first clock signals for selectively boosting the potentials at said plurality of nodes and selectively discharging said potentials toward said diode circuit, each of said plurality of boosting stages including

a second field effect transistor connected between two nodes selected from said plurality of nodes and having

a second back gate electrically isolated from said first back gate, connected to one of said two nodes farther from said one of said plurality of nodes than the other of said two nodes and supplied with a second potential independently varied for restricting said back-gate biasing effect in said second field effect transistor and

a second gate electrode connected to said one of said two nodes and responsive to said second potential for creating a second current path from said one of said two nodes to said other of said two nodes, and

a first capacitor connected to said other of said two nodes and responsive to one of said first clock signals for boosting the potential at said other of said two nodes,

in which said each of said plurality of boosting stages further includes

a second capacitor connected to said second gate electrode and responsive to one of second clock signals for periodically boosting a potential level at said second gate electrode, and

a third field effect transistor connected between said second gate electrode and said one of said two nodes and responsive to the potential level at said other of said two nodes for connecting said second gate electrode to said one of said two nodes,

in which said each of said plurality of boosting stages further includes

a fourth field effect transistor connected between said one of said two nodes and said second gate electrode and responsive to the potential level at said second gate electrode for connecting said second gate electrode to said one of said two nodes.

13. The charge pump as set forth in claim 12, in which said first field effect transistor, said second field effect transistor, said third field effect transistor and said forth field effect transistor are operative in an enhancement mode for creating conductive channels featured by a donor.