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Charge pump for generating negative voltage without change of threshold due to undesirable back-gate biasing effect

  • US 6,175,264 B1
  • Filed: 03/12/1999
  • Issued: 01/16/2001
  • Est. Priority Date: 03/16/1998
  • Status: Expired due to Term
First Claim
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1. A charge pump circuit comprising:

  • a plurality of nodes independently variable in potential level;

    a diode circuit including a first field effect transistor connected between one of said plurality of nodes and a source of constant voltage and having a diode connected between a back gate and a positive power supply line;

    the first back gate also being connected to said one of said plurality of nodes and supplied with a first potential for restricting a back-gate biasing effect in said first field effect transistor and a first gate electrode connected to said one of said plurality of nodes and responsive to said first potential for creating a first current path from said one of said plurality of nodes to said source of constant voltage; and

    a plurality of boosting stages connected in series between said plurality of nodes and responsive to first clock signals for selectively boosting the potentials at said plurality of nodes and selectively discharging said potentials toward said diode circuit, each of said plurality of boosting stages including a second field effect transistor connected between two nodes selected from said plurality of nodes and having a second back gate connected to the positive power supply line via a second diode and electrically isolated from said first back gate, connected to one of said two nodes farther from said one of said plurality of nodes than the other of said two nodes and supplied with a second potential independently varied for restricting said back-gate biasing effect in said second field effect transistor and a second gate electrode connected to said one of said two nodes and responsive to said second potential for creating a second current path from said one of said two nodes to said other of said two nodes, and a first capacitor connected to said other of said two nodes and responsive to one of said first clock signals for boosting the potential at said other of said two nodes.

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