Method and apparatus of high dynamic range image sensor with individual pixel reset

• US 6,175,383 B1
• Filed: 11/07/1996
• Issued: 01/16/2001
• Est. Priority Date: 11/07/1996
• Status: Expired due to Term

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Yadid-Pecht, Orly, Fossum, Eric R., Pain, Bedabrata
• Primary Examiner(s): Garber, Wendy
• Assistant Examiner(s): Harrington, Alicia M.
• Application Number:
  US08/744,956
• Time in Patent Office: 1,531 Days
• Field of Search: 348/257, 348/291, 348/292, 348/296, 348/297, 348/301, 348/302, 348/306, 348/307, 348/308
• US Class Current: 348/302
• CPC Class Codes: H04N 25/533 by using differing integration times for different sensor regions
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

A wide dynamic range image sensor provides individual pixel reset to vary the integration time of individual pixels. The integration time of each pixel is controlled by column and row reset control signals which activate a logical reset transistor only when both signals coincide for a given pixel.

Claims

1. An imaging device comprising:

an array of pixel cells, arranged in columns and rows, each pixel cell comprising a photo-sensitive element capable of generating an output indicative of incoming electromagnetic radiation, a logical reset transistor having a source coupled to control said photo-sensitive element and a drain biased at a potential, a row reset transistor having a gate to receive a row reset signal, a drain to receive a column reset signal, and a source connected to a gate of said logical reset transistor to reset said photo-sensitive element when both said row and column reset signals are high;

a control circuit coupled to control said array;

a row reset control element coupled between the control circuit and each pixel cell in said array to produce said row reset signal; and

a column reset control element coupled between said control circuit and each pixel cell in said array to produce said column reset signal, wherein said row and column reset control elements are operable to randomly reset any pixel cell independently.

2. An imaging device as in claim 1 wherein each of the row and column reset control elements includes a decoder to decode a respective control signal from said control circuit.

3. An imaging device as in claim 1 further including a readout circuit that comprises a field effect source follower output transistor.

4. An imaging device as in claim 3, further comprising:

a row readout control circuit coupled to each row of pixel cells and selecting individual rows for readout; and

a column readout control circuit coupled to each column of pixel cells to select a column for output.

5. An imaging device as in claim 3 wherein said readout circuit includes a reset output terminal to produce a signal indicative of an output level of said photo-sensitive element during reset and a sample output terminal to produce a signal indicative of an output level of said photo-sensitive element after completing an integration.

6. An imaging device as in claim 1 further comprising a monolithic semiconductor integrated circuit substrate on which said array of pixel cells, said control circuit, said row and column reset control elements are formed.

7. An imaging device as in claim 1 further comprising a readout circuit coupled to said array and said control circuit, wherein said control circuit is operable to modify a timing of at least one of said row and column reset signals in response to a readout circuit output, whereby the dynamic range of the imaging device is modified.

8. An imaging device, comprising:

a substrate; and

an array of pixel cells formed on said substrate and arranged in columns and rows, each pixel cell comprising;

a photo sensor responsive to input radiation to produce a pixel output signal,

a first transistor having a source coupled to said photo sensor and a drain coupled to a bias potential, and

a second transistor having a source coupled to a gate of said first transistor, and a gate coupled to receive a row reset signal, and a drain coupled to receive a column reset signal, wherein said first transistor is on to reset said photo sensor when both said column reset and row reset signals are high.

9. A device as in claim 8, wherein said photo sensor includes a photodiode.

10. A device as in claim 8, wherein said photo sensor includes a photogate.

11. A device as in claim 8, further comprising a readout circuit coupled to said photo sensor to receive said pixel output signal.

12. A device as in claim 11, further comprising a control circuit coupled to said readout circuit and said array to receive an output signal from each of said pixel cells, said control circuit operable to adjust an integration time of a pixel cell by controlling at least one of said row reset and column reset signals in response to an output signal from said pixel cell.

13. A device as in claim 8, wherein each of said pixel cells is an active pixel cell.