Content addressable memory device

• US 6,175,514 B1
• Filed: 08/27/1999
• Issued: 01/16/2001
• Est. Priority Date: 01/15/1999
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Fast-Chip, Inc.
• Inventors: Croft, Walter E., Henderson, Alex E.
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US09/384,810
• Time in Patent Office: 508 Days
• Field of Search: 365/49, 365/154, 365/155, 365/156
• US Class Current: 365/49.17
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
• CPC Class Codes: G11C 15/04 using semiconductor elements
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: Y10S 623/915 Method or apparatus for preparing biological material

Abstract

A content addressable memory device is provided which may include a novel CAM cell structure which reduces the total power dissipated by the CAM and improves the match time for the CAM. The novel CAM cell structure may include a CMOS implemented compare cell and a wide AND gate which combines the match decisions for each CAM cell into a match decision. The CAM cell structure may be implemented in a variety of different CAM devices, including dual port CAM devices, CAM devices with individual bit masking, event co-processors and database co-processors.

Claims

1. An apparatus for comparing at least one bit stored in a content addressable memory device against at least one compare bit, comprising:

a first input for receiving the stored bit from the content addressable memory device,

a second input for receiving the compare bit,

a compare logic unit adapted to perform a compare between the compare bit and the stored bit and,

an output which actively generates a match signal when the compare bit and the stored bit match and actively generates a non-match signal when the compare bit does not match the stored bit, for reducing power dissipation by eliminating pre-charge and pull-up functions.

2. The apparatus of claim 1 further comprising a third input for receiving a mask bit and configured to generate a match signal on output if the mask bit indicates that the stored bit not be compared.

3. The apparatus of claim 1 further comprising a wide logic gate adapted to receive the output signal from a plurality of bit comparisons to provide a compare signal which is actively high when the plurality of output signals are all match signals, and is actively low when the plurality of output signals are not all match signals.

4. The apparatus of claim 3 wherein the wide logic gate comprises a plurality of logic gates arranged in stages and geographically distributed throughout the content addressable memory device to further reduce power dissipation.

5. The apparatus of claim 4 wherein the stages alternate between NAND and NOR logic gates to form a wide AND gate.

6. The apparatus of claim 1 further comprising a selectable stacker input configured to selectably group and test a plurality of compare signals for uniform matching.

7. The apparatus of claim 1 further comprising a plurality of inputs to receive additional compare bits, and a corresponding number of compare logic units and outputs to indicate whether the additional compare bits match the same stored bit.

8. The apparatus of claim 1 further comprising a management logic unit adapted to selectable disable the compare logic unit and output.

9. A content addressable memory (CAM) cell for a high density CAM array of one or more CAM cells, comprising:

a memory cell for storing a data bit comprising at least one input for receiving the data bit and at least one output for transmitting the data bit,

a compare cell for comparing a compare bit with the data bit, the compare cell comprising an input coupled to receive the data bit from the memory cell, an input coupled to receive the compare bit, and an output for asserting a high signal when the compare bit matches the data bit, and asserting a low signal when the compare bit does not match the data bit, whereby power dissipation is reduced by eliminating pre-charge and pull-up functions and,

at least one logic gate coupled to receive the output of the compare cell and capable of cooperating with other CAM cell logic gates to determine if one or more CAM cells contain matches.

10. The apparatus of claim 9 wherein the logic gates cooperate with other CAM cell logic gates to form a wide logic gate corresponding to a data entry, the wide logic gate being geographically distributed across the CAM device to further reduce power dissipation problems.

11. The apparatus of claim 10 wherein the logic gates which cooperate to form the wide logic gate are arranged in hierarchical layers of alternating NAND and NOR functionality.

12. The apparatus of claim 9 wherein the compare cell utilizes CMOS transistors to provide a denser transistor pattern for implementation of a sea-of-gates array.

13. The apparatus of claim 11 wherein the logic gates associated with the first layer of the wide logic gate for the same data entry are physically located near each other along with corresponding memory cells and compare cells to facilitate shorter routing requirements and lower power dissipation.

14. A method for comparing at least one stored bit in a content addressable memory device against at least one compare bit comprising the steps of:

reading the compare bit,

reading the stored bit,

comparing the compare bit against the stored data bit and,

generating a compare signal based on the bit comparison wherein the compare signal is actively drawn high when the compare bit and stored bit match, and actively drawn low when the compare bit and stored bit do not match, and whereby the step of generating a compare signal reduces power dissipation by eliminating pre-charge and pull-up functions.

15. The method of claim 14 further comprising the step of:

combining a plurality of compare signals corresponding to a plurality of stored bits to determine if a larger data set formed from the stored bits matches a compare set formed from the compare bits and generating an aggregate signal.

16. The method of claim 15 wherein the step of combining the plurality of compare signals further comprises performing the combination in multiple stages to further reduce power dissipation and to increase expandability of the CAM device.

17. The method of claim 16 where the multiple stages of the combination alternate between NAND-ing and NOR-ing the compare signals until all desired compare signals are combined into the aggregate signal.

18. The method of claim 15 further comprising the step of:

providing a user selectable stacker input to compare a plurality of data sets against a plurality of corresponding compare sets, by combining the aggregate signals according to the stacker input to generate a match signal indicating whether the plurality of data sets matches the corresponding compare sets.

19. The method of claim 14 further comprising the step of:

reading a masking bit and drawing the compare signal high when the masking bit indicates that the stored bit not be compared.