Semiconductor integrated circuit with low-power bus structure and system for composing low-power bus structure

• US 6,175,886 B1
• Filed: 08/28/1998
• Issued: 01/16/2001
• Est. Priority Date: 08/28/1997
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Usami, Kimiyoshi
• Primary Examiner(s): Etienne, Ario
• Application Number:
  US09/143,544
• Time in Patent Office: 872 Days
• Field of Search: 710/100, 710/126, 710/129, 710/131
• US Class Current: 710/100
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A bus (9) is structured to reduce Dower consumption. The bus (9) is used to transfer data among functional blocks (1, 3, 5, 7) formed on an LSI chip. The bus is divided into subsections (9a, 9b, 9c). A pair of the functional blocks (1, 7) whose frequency of mutual data transfer is high is connected to the same subsection (9b). Connectors (29, 31) are inserted between the subsections so that the subsections may optionally electrically be connected to and disconnected from each other. When data is transferred between the functional blocks whose frequency of mutual data transfer is high, the subsection to which the functional blocks in question are connected is electrically disconnected by the connectors from the other subsections.

Claims

1. A semiconductor integrated circuit comprising:

a bus divided into subsections;

functional blocks for transferring data among themselves through the bus;

connection circuit for connecting adjacent two of the subsections to each other in response to a control signal that indicates that data is to be transferred between the two subsections,

wherein said connection circuit includes a pair of buffer circuits for switchingly transferring a signal from one of the adjacent subsections to the other adjacent subsection or vice versa; and

means for grouping the functional blocks on the basis of the frequencies of mutual data transfer performed among said functional blocks such that a group of functional blocks whose frequency of mutual data transfer is high are connected to one of the subsections.

2. The semiconductor integrated circuit of claim 1, wherein those of the functional blocks whose frequency of mutual data transfer is high are connected to one of the subsections.

3. The semiconductor integrated circuit of claim 1, wherein the connection circuit is a bidirectional bus driver having:

first and second control input terminals controlled independently of each other; and

first and second data input/output (I/O) terminals connected to the adjacent subsections, for inputting and outputting data,

the bidirectional bus driver transferring data from the first data I/O terminal to the second data I/O terminal if the first control input terminal receives a first level and the second control input terminal a second level, and from the second data I/O terminal to the first data I/O terminal if the first control input terminal receives the second level and the second control input terminal the first level.

4. The semiconductor integrated circuit of claim 3, wherein the bidirectional bus driver has:

a first tri-state buffer circuit having an input terminal connected to the first data I/O terminal, an output terminal connected to the second data I/O terminal, and a control terminal connected to the first control input terminal; and

a second tri-state buffer circuit cross-coupled with the first tri-state buffer circuit, having an output terminal connected to the first data I/O terminal, an input terminal connected to the second data I/O terminal, and a control terminal connected to the second control input terminal.

5. The semiconductor integrated circuit of claim 1, wherein the bidirectional bus driver is a transfer gate.

6. The semiconductor integrated circuit of claim 1, wherein the semiconductor integrated circuit is for portable information equipment.

7. The semiconductor integrated circuit of claim 1, wherein the number of the subsections is at least three, and each of the subsections is connected to a common node through a connection circuit.

8. The semiconductor integrated circuit of claim 1, wherein the bus comprises orthogonal bus lines divided into subsections in which two of the subsections transfer data between them by disconnecting the remaining subsections from the data transferring subsections.

9. A system for composing a bus structure of a semiconductor integrated circuit, the bus structure having a bus divided into subsections, each having a small capacitance, functional blocks for transferring data among themselves through the bus, and a connection circuit for connecting adjacent two of the subsections to each other and realizing mutual data transfer between them in response to a control signal, the system comprising:

means for reading connection description for the functional blocks and timing restraints for data transfer carried out between the functional blocks through the bus;

means for analyzing the frequencies of mutual data transfer made among the functional blocks through the bus, grouping the functional blocks on the basis of the frequencies such that the functional blocks with a high frequency of mutual data transfer are connected to the same group, and connecting the functional-block groups to the subsections, respectively;

means for inserting the connection circuit between adjacent ones of the subsections means for creating control logic for the connection circuits; and

means for outputting connection description involving the inserted connection circuits, information for physical locations where the connection circuits are inserted, and the control logic for the connection circuits.