Processor including a combined parallel debug and trace port and a serial port
First Claim
1. A processor comprising:
- a processor core;
a parallel trace port providing trace information indicating instruction execution flow in said processor core;
a parallel debug port providing for sending and receiving of debug information between a debug host controller and said processor;
a serial debug port providing for transmission of debug information between said debug host controller and said processor;
wherein operation of said trace port and parallel debug port are mutually exclusive;
wherein the parallel debug port is enabled through said serial debug port; and
wherein said parallel debug port operates synchronously to a clock provided to said serial debug port.
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Accused Products
Abstract
A processor provides trace capability. Trace information can be provided over a communication port that is operable both as a trace port and as a parallel debug port. The trace port provides trace information indicating instruction execution flow in the processor core. The operation of the communication port as a trace port and as a parallel debug port is mutually exclusive. The parallel debug port provides for transmission of debug information between a debug host controller and the processor. The parallel debug port and the trace port physically share pins. Bus request and grant signals are provided between the parallel debug port and a debug host controller to ensure that collisions do not occur between use by the trace port and the debug host controller. A separate serial debug port is also provided which can be used to enable the parallel debug port.
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Citations
17 Claims
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1. A processor comprising:
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a processor core;
a parallel trace port providing trace information indicating instruction execution flow in said processor core;
a parallel debug port providing for sending and receiving of debug information between a debug host controller and said processor;
a serial debug port providing for transmission of debug information between said debug host controller and said processor;
wherein operation of said trace port and parallel debug port are mutually exclusive;
wherein the parallel debug port is enabled through said serial debug port; and
wherein said parallel debug port operates synchronously to a clock provided to said serial debug port.
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2. A processor comprising:
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a processor core;
a parallel trace port providing trace information indicating instruction execution flow in said processor core;
a parallel debug port providing for sending and receiving of debug information between a debug host controller and said processor; and
wherein operation of said trace port and parallel debug port are mutually exclusive; and
whereinsaid trace port provides a trace valid signal indicating when said trace information provided from said trace port is valid; and
wherein said trace port further includes a trace clock to which said trace data is synchronized.
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3. A method of operating a processor which includes a processor core, and a communication port selectably operable as one of a trace port and a parallel debug port, comprising:
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selectably operating said communication port as a trace port to provide trace information over said trace port;
stopping operation of said processor core;
enabling operation of said communication port as said parallel debug port by writing to a control register on said processor;
writing debug commands and data to registers on said processor via said parallel debug port;
said trace port providing a trace valid signal line indicating whether said trace information provided from said trace port is valid; and
said trace port further including a trace clock to which said trace information is synchronized.
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4. A method of operating a processor which includes a processor core, and a communication port selectably operable as one of a trace port and a parallel debug port, comprising:
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selectably operating said communication port as a trace port to provide trace information over said trace port;
stopping operation of said processor core;
enabling operation of said communication port as said parallel debug port by writing to a control register on said processor; and
writing debug commands and data to registers on said processor via said parallel debug port; and
wherein said parallel debug port operates synchronously to a clock provided to a serial debug port on said processor.
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5. A processor comprising:
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a processor core;
a serial debug port coupled to send and receive debug information between a debug host controller coupled to the processor and said processor; and
a communication port, configured to selectably operate as one of, a parallel trace port providing trace information indicating instruction execution flow in said processor core; and
a parallel debug port coupled to send and receive debug information between the debug host controller and said processor; and
wherein a majority of output terminals of said trace port are shared with said parallel debug port. - View Dependent Claims (6, 7, 8, 9, 10)
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11. A method of operating a processor which includes a processor core, a serial port and a communication port selectably operable as one of a trace port and a parallel debug port, comprising:
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selectably operating said communication port as said trace port to supply trace information over said trace port, said trace information being synchronized to a trace clock;
enabling operation of said communication port as said parallel debug port by writing to a control register on said processor through the serial debug port; and
communicating debug information over said parallel debug port in synchronism with a serial port clock. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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Specification