Method and system for selecting sizes of components for integrated circuits

• US 6,175,949 B1
• Filed: 03/24/1998
• Issued: 01/16/2001
• Est. Priority Date: 03/24/1998
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Tretz, Christophe Robert, Gristede, George D., Hwang, Wei
• Primary Examiner(s): Lintz, Paul R.
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US09/046,826
• Time in Patent Office: 1,029 Days
• Field of Search: 716/2, 716/6, 716/1, 716/12, 716/19
• US Class Current: 716/135
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Abstract

A method of automatically selecting object size in an integrated circuit includes the steps of providing a circuit topology having objects disposed therein, inputting equations associated with the objects to provide sizing adjustment for the objects, assigning parameter values in the equations based on physical constraints of the circuit for one or more objects, selecting one or more objects to be sized, evaluating cones of influence for the objects selected to identify influenced objects influenced by a change in the selected object and computing for each selected object and influenced objects, a size in accordance with the associated equation until a user defined criteria is achieved for the circuit. A system for performing the method of the present invention is also described.

Claims

1. A method of automatically selecting object size in an integrated circuit, by employing a graphical user interface, comprising the steps of:

providing a circuit topology on a graphical user interface having objects disposed therein;

inputting equations associated with the objects such that each object has an individually assigned parametric equation which controls a size of the object to provide sizing adjustment for each object;

assigning parameter values in the equations based on physical constraints of the circuit for one or more objects;

selecting one or more objects to be sized by individually selecting the one or more objects on the graphical user interface; and

computing for each selected object and objects influenced by the selected object, a size in accordance with the associated equation until a user defined criteria is achieved for the circuit.

2. The method as recited in claim 1, further comprises the step of outputting a topology with object sizes modified according to the associated equations.

3. The method as recited in claim 1, wherein the objects include transistors.

4. The method as recited in claim 1, wherein the objects include capacitors and further comprising the step of modeling the capacitors as transistors by adjusting a capacitance load of the capacitors in accordance with a capacitance conversion factor.

5. The method as recited in claim 1, wherein the objects include hierarchical circuits.

6. The method as recited in claim 1, wherein the objects include vectorized hierarchical circuits.

7. The method as recited in claim 1, wherein the objects include parameterized cells.

8. The method as recited in claim 1, further comprises the step of calculating node loads for analyzing the circuit in accordance with the user defined criteria.

9. The method as recited in claim 1, wherein the physical constraints include gain and the parameter values include a multiplier.

10. The method as recited in claim 1, further comprises the step of evaluating cones of influence for the objects selected to identify influenced objects that are influenced by a change in the selected object.

11. A program storage device readable by machine, tangibly embodying a program of instructions executable by machine to perform method steps for automatically selecting object size in an integrated circuit, according to claim 1.

18. The method as recited in claim 10, wherein the physical constraints include gain and the parameter values include a multiplier.

19.The method as recited in claim 12, further comprises the step of outputting a topology with objects in the circuit having modified sizes.

20. A program storage device readable by machine, tangibly embodying a program of instructions executable by machine to perform method steps for automatically selecting object size in an integrated circuit, according to claim 10.

12. A method of automatically selecting object size in an integrated circuit, by employing a graphical user interface, comprising the steps of:

providing a circuit topology on a graphical user interface having objects disposed therein;

inputting equations associated with the objects such that each object has an individually assigned parametric equation which controls a size of the object to provide sizing adjustment for each object;

assigning parameter values in the equations based on physical constraints of the circuit for one or more objects;

locking one or more objects in the circuit by individually selecting the one or more objects on the graphical user interface to prevent sizing adjustment to locked objects thereby creating an unlocked subset of objects;

evaluating cones of influence for the subset of objects to identify influenced objects influenced by a change in a selected object; and

computing for each of the subset of objects and influenced objects, a size in accordance with the associated equation until a user defined criteria is achieved for the circuit.

13. The method as recited in claim 12, wherein the objects include capacitors and further comprising the step of modeling the capacitors as transistors by adjusting a capacitance load of the capacitors in accordance with a capacitance conversion factor.

14. The method as recited in claim 12, wherein the objects include hierarchical circuits and subcircuits.

15. The method as recited in claim 12, wherein the objects include vectorized hierarchical circuits.

16. The method as recited in claim 12, wherein the objects include parameterized cells.

17. The method as recited in claim 12, further comprises the step of calculating node loads for analyzing the circuit in accordance with the user defined criteria.

19. The method as recited in claim 12, wherein the objects include transistors.

21. A system for automatically selecting object size in an integrated circuit, by employing a graphical user interface, comprising:

a circuit topology having objects disposed therein and displayed on a graphical user interface;

means for inputting equations associated with the objects such that each object has an individually assigned parametric equation which controls a size of the object to provide sizing adjustment for each object, the equations including parameter values for one or more objects based on physical constraints of the circuit;

means for selecting one or more objects to be sized by individually selecting the one or more objects on the graphical user interface;

means for evaluating cones of influence for the objects selected to identify influenced objects influenced by a change in the selected object; and

means for computing for each selected object and influenced objects, a size in accordance with the associated equation until a user defined criteria is achieved for the circuit.

22. The system as recited in claim 22, further comprises means for outputting a topology with objects in the circuit sized in accordance with the associated equations.

23. The system as recited in claim 23, wherein the objects include vectorized hierarchical circuits.

24. The system as recited in claim 23, wherein the objects include parameterized cells.

25. The method as recited in claim 23, wherein the physical constraints include values for a gain of the objects and the parameter is a multiplier.

26. The method as recited in claim 23, wherein the means for evaluating cones of influence for the objects includes a processor for analyzing the circuit to identify influenced objects.

27. The system as recited in claim 23, wherein the objects include transistors.

28. The system as recited in claim 23, wherein the objects include capacitors and further comprising a capacitance conversion factor for modeling capacitance loads as transistors.

29. The system as recited in claim 23, wherein the objects include hierarchical circuits.